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Commit a843ed3f authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
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clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs 



The parent clock of the Audio DMACs is the "ZS" AXI bus clock, which
maps to S3D1 on R-Car H3 ES1.x.
All module clocks must be sorted by clock ID.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: default avatarKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
parent 6c8a9312

drivers/clk/renesas/r8a7795-cpg-mssr.c

+2 −2
Original line number Diff line number Diff line
@@ -142,8 +142,8 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { 
	DEF_MOD("rwdt0",		 402,	R8A7795_CLK_R),

	DEF_MOD("intc-ex",		 407,	R8A7795_CLK_CP),

	DEF_MOD("intc-ap",		 408,	R8A7795_CLK_S3D1),

	DEF_MOD("audmac0",		 502,	R8A7795_CLK_S3D4),

	DEF_MOD("audmac1",		 501,	R8A7795_CLK_S3D4),

	DEF_MOD("audmac1",		 501,	R8A7795_CLK_S3D1),

	DEF_MOD("audmac0",		 502,	R8A7795_CLK_S3D1),

	DEF_MOD("drif7",		 508,	R8A7795_CLK_S3D2),

	DEF_MOD("drif6",		 509,	R8A7795_CLK_S3D2),

	DEF_MOD("drif5",		 510,	R8A7795_CLK_S3D2),