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Commit a82256bc authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'drm-intel-next-2017-05-29' of git://anongit.freedesktop.org/git/drm-intel into drm-next 

More stuff for 4.13:

- skl+ wm fixes from Mahesh Kumar
- some refactor and tests for i915_sw_fence (Chris)
- tune execlist/scheduler code (Chris)
- g4x,g33 gpu reset improvements (Chris, Mika)
- guc code cleanup (Michal Wajdeczko, Michał Winiarski)
- dp aux backlight improvements (Puthikorn Voravootivat)
- buffer based guc/host communication (Michal Wajdeczko)

* tag 'drm-intel-next-2017-05-29' of git://anongit.freedesktop.org/git/drm-intel: (253 commits)
  drm/i915: Update DRIVER_DATE to 20170529
  drm/i915: Keep the forcewake timer alive for 1ms past the most recent use
  drm/i915/guc: capture GuC logs if FW fails to load
  drm/i915/guc: Introduce buffer based cmd transport
  drm/i915/guc: Disable send function on fini
  drm: Add definition for eDP backlight frequency
  drm/i915: Drop AUX backlight enable check for backlight control
  drm/i915: Consolidate #ifdef CONFIG_INTEL_IOMMU
  drm/i915: Only GGTT vma may be pinned and prevent shrinking
  drm/i915: Serialize GTT/Aperture accesses on BXT
  drm/i915: Convert i915_gem_object_ops->flags values to use BIT()
  drm/i915/selftests: Silence compiler warning in igt_ctx_exec
  drm/i915/guc: Skip port assign on first iteration of GuC dequeue
  drm/i915: Remove misleading comment in request_alloc
  drm/i915/g33: Improve reset reliability
  Revert "drm/i915: Restore lost "Initialized i915" welcome message"
  drm/i915/huc: Update GLK HuC version
  drm/i915: Check for allocation failure
  drm/i915/guc: Remove action status and statistics from debugfs
  drm/i915/g4x: Improve gpu reset reliability
  ...
parents 1afc4544 cd9f4688

drivers/gpu/drm/i915/Kconfig.debug

+12 −0
Original line number Diff line number Diff line
@@ -61,6 +61,18 @@ config DRM_I915_SW_FENCE_DEBUG_OBJECTS 


          If in doubt, say "N".



config DRM_I915_SW_FENCE_CHECK_DAG

        bool "Enable additional driver debugging for detecting dependency cycles"

        depends on DRM_I915

        default n

        help

          Choose this option to turn on extra driver debugging that may affect

          performance but will catch some internal issues.



          Recommended for driver developers only.



          If in doubt, say "N".



config DRM_I915_SELFTEST

	bool "Enable selftests upon driver load"

	depends on DRM_I915

drivers/gpu/drm/i915/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ i915-y := i915_drv.o \ 
	  i915_params.o \

	  i915_pci.o \

          i915_suspend.o \

	  i915_syncmap.o \

	  i915_sw_fence.o \

	  i915_sysfs.o \

	  intel_csr.o \
@@ -57,6 +58,7 @@ i915-y += i915_cmd_parser.o \ 


# general-purpose microcontroller (GuC) support

i915-y += intel_uc.o \

	  intel_guc_ct.o \

	  intel_guc_log.o \

	  intel_guc_loader.o \

	  intel_huc.o \

drivers/gpu/drm/i915/dvo_ch7017.c

+2 −2
Original line number Diff line number Diff line
@@ -280,10 +280,10 @@ static void ch7017_mode_set(struct intel_dvo_device *dvo, 
			(0 << CH7017_PHASE_DETECTOR_SHIFT);

	} else {

		outputs_enable = CH7017_LVDS_CHANNEL_A | CH7017_CHARGE_PUMP_HIGH;

		lvds_pll_feedback_div = CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED |

		lvds_pll_feedback_div =

			CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED |

			(2 << CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT) |

			(3 << CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT);

		lvds_pll_feedback_div = 35;

		lvds_control_2 = (3 << CH7017_LOOP_FILTER_SHIFT) |

			(0 << CH7017_PHASE_DETECTOR_SHIFT);

		if (1) { /* XXX: dual channel panel detection.  Assume yes for now. */

drivers/gpu/drm/i915/gvt/scheduler.c

+6 −6
Original line number Diff line number Diff line
@@ -69,8 +69,7 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload) 
	gvt_dbg_sched("ring id %d workload lrca %x", ring_id,

			workload->ctx_desc.lrca);



	context_page_num = intel_lr_context_size(

			gvt->dev_priv->engine[ring_id]);

	context_page_num = gvt->dev_priv->engine[ring_id]->context_size;



	context_page_num = context_page_num >> PAGE_SHIFT;
@@ -181,6 +180,7 @@ static int dispatch_workload(struct intel_vgpu_workload *workload) 
	struct intel_engine_cs *engine = dev_priv->engine[ring_id];

	struct drm_i915_gem_request *rq;

	struct intel_vgpu *vgpu = workload->vgpu;

	struct intel_ring *ring;

	int ret;



	gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
@@ -199,8 +199,9 @@ static int dispatch_workload(struct intel_vgpu_workload *workload) 
	 * shadow_ctx pages invalid. So gvt need to pin itself. After update

	 * the guest context, gvt can unpin the shadow_ctx safely.

	 */

	ret = engine->context_pin(engine, shadow_ctx);

	if (ret) {

	ring = engine->context_pin(engine, shadow_ctx);

	if (IS_ERR(ring)) {

		ret = PTR_ERR(ring);

		gvt_vgpu_err("fail to pin shadow context\n");

		workload->status = ret;

		mutex_unlock(&dev_priv->drm.struct_mutex);
@@ -330,8 +331,7 @@ static void update_guest_context(struct intel_vgpu_workload *workload) 
	gvt_dbg_sched("ring id %d workload lrca %x\n", ring_id,

			workload->ctx_desc.lrca);



	context_page_num = intel_lr_context_size(

			gvt->dev_priv->engine[ring_id]);

	context_page_num = gvt->dev_priv->engine[ring_id]->context_size;



	context_page_num = context_page_num >> PAGE_SHIFT;

drivers/gpu/drm/i915/i915_cmd_parser.c

+5 −5
Original line number Diff line number Diff line
@@ -1166,8 +1166,8 @@ static bool check_cmd(const struct intel_engine_cs *engine, 
				find_reg(engine, is_master, reg_addr);



			if (!reg) {

				DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (exec_id=%d)\n",

						 reg_addr, *cmd, engine->exec_id);

				DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (%s)\n",

						 reg_addr, *cmd, engine->name);

				return false;

			}
@@ -1222,11 +1222,11 @@ static bool check_cmd(const struct intel_engine_cs *engine, 
				desc->bits[i].mask;



			if (dword != desc->bits[i].expected) {

				DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (exec_id=%d)\n",

				DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (%s)\n",

						 *cmd,

						 desc->bits[i].mask,

						 desc->bits[i].expected,

						 dword, engine->exec_id);

						 dword, engine->name);

				return false;

			}

		}
@@ -1284,7 +1284,7 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine, 


		if (*cmd == MI_BATCH_BUFFER_END) {

			if (needs_clflush_after) {

				void *ptr = ptr_mask_bits(shadow_batch_obj->mm.mapping);

				void *ptr = page_mask_bits(shadow_batch_obj->mm.mapping);

				drm_clflush_virt_range(ptr,

						       (void *)(cmd + 1) - ptr);

			}