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Commit a7d80d01 authored by Michael Neuling's avatar Michael Neuling Committed by Paul Mackerras
Browse files

KVM: PPC: Book3S HV: Add get/set_one_reg for new TM state 



This adds code to get/set_one_reg to read and write the new transactional
memory (TM) state.

Signed-off-by: default avatarMichael Neuling <mikey@neuling.org>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
Acked-by: default avatarScott Wood <scottwood@freescale.com>
parent e4e38121

arch/powerpc/kvm/book3s_hv.c

+125 −22
Original line number Diff line number Diff line
@@ -879,17 +879,6 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id, 
	case KVM_REG_PPC_IAMR:

		*val = get_reg_val(id, vcpu->arch.iamr);

		break;

#ifdef CONFIG_PPC_TRANSACTIONAL_MEM

	case KVM_REG_PPC_TFHAR:

		*val = get_reg_val(id, vcpu->arch.tfhar);

		break;

	case KVM_REG_PPC_TFIAR:

		*val = get_reg_val(id, vcpu->arch.tfiar);

		break;

	case KVM_REG_PPC_TEXASR:

		*val = get_reg_val(id, vcpu->arch.texasr);

		break;

#endif

	case KVM_REG_PPC_FSCR:

		*val = get_reg_val(id, vcpu->arch.fscr);

		break;
@@ -970,6 +959,69 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id, 
	case KVM_REG_PPC_PPR:

		*val = get_reg_val(id, vcpu->arch.ppr);

		break;

#ifdef CONFIG_PPC_TRANSACTIONAL_MEM

	case KVM_REG_PPC_TFHAR:

		*val = get_reg_val(id, vcpu->arch.tfhar);

		break;

	case KVM_REG_PPC_TFIAR:

		*val = get_reg_val(id, vcpu->arch.tfiar);

		break;

	case KVM_REG_PPC_TEXASR:

		*val = get_reg_val(id, vcpu->arch.texasr);

		break;

	case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31:

		i = id - KVM_REG_PPC_TM_GPR0;

		*val = get_reg_val(id, vcpu->arch.gpr_tm[i]);

		break;

	case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63:

	{

		int j;

		i = id - KVM_REG_PPC_TM_VSR0;

		if (i < 32)

			for (j = 0; j < TS_FPRWIDTH; j++)

				val->vsxval[j] = vcpu->arch.fp_tm.fpr[i][j];

		else {

			if (cpu_has_feature(CPU_FTR_ALTIVEC))

				val->vval = vcpu->arch.vr_tm.vr[i-32];

			else

				r = -ENXIO;

		}

		break;

	}

	case KVM_REG_PPC_TM_CR:

		*val = get_reg_val(id, vcpu->arch.cr_tm);

		break;

	case KVM_REG_PPC_TM_LR:

		*val = get_reg_val(id, vcpu->arch.lr_tm);

		break;

	case KVM_REG_PPC_TM_CTR:

		*val = get_reg_val(id, vcpu->arch.ctr_tm);

		break;

	case KVM_REG_PPC_TM_FPSCR:

		*val = get_reg_val(id, vcpu->arch.fp_tm.fpscr);

		break;

	case KVM_REG_PPC_TM_AMR:

		*val = get_reg_val(id, vcpu->arch.amr_tm);

		break;

	case KVM_REG_PPC_TM_PPR:

		*val = get_reg_val(id, vcpu->arch.ppr_tm);

		break;

	case KVM_REG_PPC_TM_VRSAVE:

		*val = get_reg_val(id, vcpu->arch.vrsave_tm);

		break;

	case KVM_REG_PPC_TM_VSCR:

		if (cpu_has_feature(CPU_FTR_ALTIVEC))

			*val = get_reg_val(id, vcpu->arch.vr_tm.vscr.u[3]);

		else

			r = -ENXIO;

		break;

	case KVM_REG_PPC_TM_DSCR:

		*val = get_reg_val(id, vcpu->arch.dscr_tm);

		break;

	case KVM_REG_PPC_TM_TAR:

		*val = get_reg_val(id, vcpu->arch.tar_tm);

		break;

#endif

	case KVM_REG_PPC_ARCH_COMPAT:

		*val = get_reg_val(id, vcpu->arch.vcore->arch_compat);

		break;
@@ -1039,17 +1091,6 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id, 
	case KVM_REG_PPC_IAMR:

		vcpu->arch.iamr = set_reg_val(id, *val);

		break;

#ifdef CONFIG_PPC_TRANSACTIONAL_MEM

	case KVM_REG_PPC_TFHAR:

		vcpu->arch.tfhar = set_reg_val(id, *val);

		break;

	case KVM_REG_PPC_TFIAR:

		vcpu->arch.tfiar = set_reg_val(id, *val);

		break;

	case KVM_REG_PPC_TEXASR:

		vcpu->arch.texasr = set_reg_val(id, *val);

		break;

#endif

	case KVM_REG_PPC_FSCR:

		vcpu->arch.fscr = set_reg_val(id, *val);

		break;
@@ -1144,6 +1185,68 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id, 
	case KVM_REG_PPC_PPR:

		vcpu->arch.ppr = set_reg_val(id, *val);

		break;

#ifdef CONFIG_PPC_TRANSACTIONAL_MEM

	case KVM_REG_PPC_TFHAR:

		vcpu->arch.tfhar = set_reg_val(id, *val);

		break;

	case KVM_REG_PPC_TFIAR:

		vcpu->arch.tfiar = set_reg_val(id, *val);

		break;

	case KVM_REG_PPC_TEXASR:

		vcpu->arch.texasr = set_reg_val(id, *val);

		break;

	case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31:

		i = id - KVM_REG_PPC_TM_GPR0;

		vcpu->arch.gpr_tm[i] = set_reg_val(id, *val);

		break;

	case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63:

	{

		int j;

		i = id - KVM_REG_PPC_TM_VSR0;

		if (i < 32)

			for (j = 0; j < TS_FPRWIDTH; j++)

				vcpu->arch.fp_tm.fpr[i][j] = val->vsxval[j];

		else

			if (cpu_has_feature(CPU_FTR_ALTIVEC))

				vcpu->arch.vr_tm.vr[i-32] = val->vval;

			else

				r = -ENXIO;

		break;

	}

	case KVM_REG_PPC_TM_CR:

		vcpu->arch.cr_tm = set_reg_val(id, *val);

		break;

	case KVM_REG_PPC_TM_LR:

		vcpu->arch.lr_tm = set_reg_val(id, *val);

		break;

	case KVM_REG_PPC_TM_CTR:

		vcpu->arch.ctr_tm = set_reg_val(id, *val);

		break;

	case KVM_REG_PPC_TM_FPSCR:

		vcpu->arch.fp_tm.fpscr = set_reg_val(id, *val);

		break;

	case KVM_REG_PPC_TM_AMR:

		vcpu->arch.amr_tm = set_reg_val(id, *val);

		break;

	case KVM_REG_PPC_TM_PPR:

		vcpu->arch.ppr_tm = set_reg_val(id, *val);

		break;

	case KVM_REG_PPC_TM_VRSAVE:

		vcpu->arch.vrsave_tm = set_reg_val(id, *val);

		break;

	case KVM_REG_PPC_TM_VSCR:

		if (cpu_has_feature(CPU_FTR_ALTIVEC))

			vcpu->arch.vr.vscr.u[3] = set_reg_val(id, *val);

		else

			r = - ENXIO;

		break;

	case KVM_REG_PPC_TM_DSCR:

		vcpu->arch.dscr_tm = set_reg_val(id, *val);

		break;

	case KVM_REG_PPC_TM_TAR:

		vcpu->arch.tar_tm = set_reg_val(id, *val);

		break;

#endif

	case KVM_REG_PPC_ARCH_COMPAT:

		r = kvmppc_set_arch_compat(vcpu, set_reg_val(id, *val));

		break;