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Commit a7686359 authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: lagoon: Update the dp clock ops for dispcc 



The dp_crypto and dp_link clocks of mdss require to use the rcg2 ops and
the cache rate flag, so update it accordingly.

While at it update the flag for LUT clock.

Change-Id: I77e2e1b2690baacfc0cae46bdd6ed926dc8ebc1a
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 22d8b200

drivers/clk/qcom/dispcc-lagoon.c

+5 −5
Original line number Diff line number Diff line
@@ -273,8 +273,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { 
		.name = "disp_cc_mdss_dp_crypto_clk_src",

		.parent_names = disp_cc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_byte2_ops,

		.flags = CLK_GET_RATE_NOCACHE,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {
@@ -303,8 +303,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { 
		.name = "disp_cc_mdss_dp_link_clk_src",

		.parent_names = disp_cc_parent_names_0,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_byte2_ops,

		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {
@@ -633,7 +633,7 @@ static struct clk_branch disp_cc_mdss_mdp_clk = { 


static struct clk_branch disp_cc_mdss_mdp_lut_clk = {

	.halt_reg = 0x1020,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x1020,

		.enable_mask = BIT(0),