Merge tag 'regmap-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap

*ST pin controller.

Each multi-function pin is controlled, driven and routed through the

PIO multiplexing block. Each pin supports GPIO functionality (ALT0)

and multiple alternate functions(ALT1 - ALTx) that directly connect

the pin to different hardware blocks.

When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and

Pull Up (PU) are driven by the related PIO block.

ST pinctrl driver controls PIO multiplexing block and also interacts with

gpio driver to configure a pin.

Required properties: (PIO multiplexing block)

- compatible	: should be "st,<SOC>-<pio-block>-pinctrl"

	like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on.

- gpio-controller : Indicates this device is a GPIO controller

- #gpio-cells	  : Should be one. The first cell is the pin number.

- st,retime-pin-mask	: Should be mask to specify which pins can be retimed.

	If the property is not present, it is assumed that all the pins in the

	bank are capable of retiming. Retiming is mainly used to improve the

	IO timing margins of external synchronous interfaces.

- st,bank-name		: Should be a name string for this bank as

			specified in datasheet.

- st,syscfg		: Should be a phandle of the syscfg node.

Example:

	pin-controller-sbc {

		#address-cells	= <1>;

		#size-cells	= <1>;

		compatible	= "st,stih415-sbc-pinctrl";

		st,syscfg	= <&syscfg_sbc>;

		ranges 		= <0 0xfe610000 0x5000>;

		PIO0: gpio@fe610000 {

			gpio-controller;

			#gpio-cells	= <1>;

			reg		= <0 0x100>;

			st,bank-name	= "PIO0";

		};

		...

		pin-functions nodes follow...

	};

Contents of function subnode node:

----------------------

Required properties for pin configuration node:

- st,pins	: Child node with list of pins with configuration.

Below is the format of how each pin conf should look like.

<bank offset mux mode rt_type rt_delay rt_clk>

Every PIO is represented with 4-7 parameters depending on retime configuration.

Each parameter is explained as below.

-bank		: Should be bank phandle to which this PIO belongs.

-offset		: Offset in the PIO bank.

-mux		: Should be alternate function number associated this pin.

		Use same numbers from datasheet.

-mode		:pin configuration is selected from one of the below values.

		IN

		IN_PU

		OUT

		BIDIR

		BIDIR_PU

-rt_type	Retiming Configuration for the pin.

		Possible retime configuration are:

		-------		-------------

		value		args

		-------		-------------

		NICLK		<delay> <clk>

		ICLK_IO		<delay> <clk>

		BYPASS		<delay>

		DE_IO		<delay> <clk>

		SE_ICLK_IO	<delay> <clk>

		SE_NICLK_IO	<delay> <clk>

- delay	is retime delay in pico seconds as mentioned in data sheet.

- rt_clk	:clk to be use for retime.

		Possible values are:

		CLK_A

		CLK_B

		CLK_C

		CLK_D

Example of mmcclk pin which is a bi-direction pull pu with retime config

as non inverted clock retimed with CLK_B and delay of 0 pico seconds:

pin-controller {

	...

	mmc0 {

		pinctrl_mmc: mmc {

			st,pins {

				mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;

				...

			};

		};

	...

	};

};

sdhci0:sdhci@fe810000{

	...

	pinctrl-names = "default";

	pinctrl-0	= <&pinctrl_mmc>;

};

struct regmap {

	struct mutex mutex;

	spinlock_t spinlock;

	unsigned long spinlock_flags;

	regmap_lock lock;

	regmap_unlock unlock;

	void *lock_arg; /* This is passed to lock/unlock functions */

	int (*read)(struct regmap *map, unsigned int reg, unsigned int *value);

	int (*write)(struct regmap *map, unsigned int reg, unsigned int value);

	int (*sync)(struct regmap *map, unsigned int min, unsigned int max);

	int (*drop)(struct regmap *map, unsigned int min, unsigned int max);

};

bool regmap_writeable(struct regmap *map, unsigned int reg);

	unsigned int window_len;

};

struct regmap_field {

	struct regmap *regmap;

	unsigned int mask;

	/* lsb */

	unsigned int shift;

	unsigned int reg;

};

#ifdef CONFIG_DEBUG_FS

extern void regmap_debugfs_initcall(void);

extern void regmap_debugfs_init(struct regmap *map, const char *name);

	return 0;

}

static struct regcache_rbtree_node *

regcache_rbtree_node_alloc(struct regmap *map, unsigned int reg)

{

	struct regcache_rbtree_node *rbnode;

	const struct regmap_range *range;

	int i;

	rbnode = kzalloc(sizeof(*rbnode), GFP_KERNEL);

	if (!rbnode)

		return NULL;

	/* If there is a read table then use it to guess at an allocation */

	if (map->rd_table) {

		for (i = 0; i < map->rd_table->n_yes_ranges; i++) {

			if (regmap_reg_in_range(reg,

						&map->rd_table->yes_ranges[i]))

				break;

		}

		if (i != map->rd_table->n_yes_ranges) {

			range = &map->rd_table->yes_ranges[i];

			rbnode->blklen = range->range_max - range->range_min

				+ 1;

			rbnode->base_reg = range->range_min;

		}

	}

	if (!rbnode->blklen) {

		rbnode->blklen = sizeof(*rbnode);

		rbnode->base_reg = reg;

	}

	rbnode->block = kmalloc(rbnode->blklen * map->cache_word_size,

				GFP_KERNEL);

	if (!rbnode->block) {

		kfree(rbnode);

		return NULL;

	}

	return rbnode;

}

static int regcache_rbtree_write(struct regmap *map, unsigned int reg,

				 unsigned int value)

{

				return 0;

			}

		}

		/* we did not manage to find a place to insert it in an existing

		 * block so create a new rbnode with a single register in its block.

		 * This block will get populated further if any other adjacent

		 * registers get modified in the future.

		/* We did not manage to find a place to insert it in

		 * an existing block so create a new rbnode.

		 */

		rbnode = kzalloc(sizeof *rbnode, GFP_KERNEL);

		rbnode = regcache_rbtree_node_alloc(map, reg);

		if (!rbnode)

			return -ENOMEM;

		rbnode->blklen = sizeof(*rbnode);

		rbnode->base_reg = reg;

		rbnode->block = kmalloc(rbnode->blklen * map->cache_word_size,

					GFP_KERNEL);

		if (!rbnode->block) {

			kfree(rbnode);

			return -ENOMEM;

		}

		regcache_rbtree_set_register(map, rbnode, 0, value);

		regcache_rbtree_set_register(map, rbnode,

					     reg - rbnode->base_reg, value);

		regcache_rbtree_insert(map, &rbtree_ctx->root, rbnode);

		rbtree_ctx->cached_rbnode = rbnode;

	}

	return 0;

}

static int regcache_default_sync(struct regmap *map, unsigned int min,

				 unsigned int max)

{

	unsigned int reg;

	for (reg = min; reg <= max; reg++) {

		unsigned int val;

		int ret;

		if (regmap_volatile(map, reg))

			continue;

		ret = regcache_read(map, reg, &val);

		if (ret)

			return ret;

		/* Is this the hardware default?  If so skip. */

		ret = regcache_lookup_reg(map, reg);

		if (ret >= 0 && val == map->reg_defaults[ret].def)

			continue;

		map->cache_bypass = 1;

		ret = _regmap_write(map, reg, val);

		map->cache_bypass = 0;

		if (ret)

			return ret;

		dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);

	}

	return 0;

}

/**

 * regcache_sync: Sync the register cache with the hardware.

 *

	const char *name;

	unsigned int bypass;

	BUG_ON(!map->cache_ops || !map->cache_ops->sync);

	BUG_ON(!map->cache_ops);

	map->lock(map->lock_arg);

	/* Remember the initial bypass state */

	}

	map->cache_bypass = 0;

	if (map->cache_ops->sync)

		ret = map->cache_ops->sync(map, 0, map->max_register);

	else

		ret = regcache_default_sync(map, 0, map->max_register);

	if (ret == 0)

		map->cache_dirty = false;

	const char *name;

	unsigned int bypass;

	BUG_ON(!map->cache_ops || !map->cache_ops->sync);

	BUG_ON(!map->cache_ops);

	map->lock(map->lock_arg);

	if (!map->cache_dirty)

		goto out;

	if (map->cache_ops->sync)

		ret = map->cache_ops->sync(map, min, max);

	else

		ret = regcache_default_sync(map, min, max);

out:

	trace_regcache_sync(map->dev, name, "stop region");

}

EXPORT_SYMBOL_GPL(regcache_sync_region);

/**

 * regcache_drop_region: Discard part of the register cache

 *

 * @map: map to operate on

 * @min: first register to discard

 * @max: last register to discard

 *

 * Discard part of the register cache.

 *

 * Return a negative value on failure, 0 on success.

 */

int regcache_drop_region(struct regmap *map, unsigned int min,

			 unsigned int max)

{

	unsigned int reg;

	int ret = 0;

	if (!map->cache_present && !(map->cache_ops && map->cache_ops->drop))

		return -EINVAL;

	map->lock(map->lock_arg);

	trace_regcache_drop_region(map->dev, min, max);

	if (map->cache_present)

		for (reg = min; reg < max + 1; reg++)

			clear_bit(reg, map->cache_present);

	if (map->cache_ops && map->cache_ops->drop)

		ret = map->cache_ops->drop(map, min, max);

	map->unlock(map->lock_arg);

	return ret;

}

EXPORT_SYMBOL_GPL(regcache_drop_region);

/**

 * regcache_cache_only: Put a register map into cache only mode

 *

	unsigned int fpos_offset;

	unsigned int reg_offset;

	/* Suppress the cache if we're using a subrange */

	if (from)

		return from;

	/*

	 * If we don't have a cache build one so we don't have to do a

	 * linear scan each time.

			reg_offset = fpos_offset / map->debugfs_tot_len;

			*pos = c->min + (reg_offset * map->debugfs_tot_len);

			mutex_unlock(&map->cache_lock);

			return c->base_reg + reg_offset;

			return c->base_reg + (reg_offset * map->reg_stride);

		}

		*pos = c->max;

		return -EINVAL;

	/* Userspace has been fiddling around behind the kernel's back */

	add_taint(TAINT_USER, LOCKDEP_NOW_UNRELIABLE);

	add_taint(TAINT_USER, LOCKDEP_STILL_OK);

	ret = regmap_write(map, reg, value);

	if (ret < 0)