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Commit a6b44888 authored by yangbo lu's avatar yangbo lu Committed by Ulf Hansson
Browse files

mmc: sdhci-esdhc: clean up register definitions 



The eSDHC register definitions in header file were messy and confusing.
This patch is to clean up these definitions.

Signed-off-by: default avatarYangbo Lu <yangbo.lu@nxp.com>
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent a8c643ad

drivers/mmc/host/sdhci-esdhc.h

+20 −19
Original line number Diff line number Diff line
@@ -24,8 +24,21 @@ 
				SDHCI_QUIRK_PIO_NEEDS_DELAY | \

				SDHCI_QUIRK_NO_HISPD_BIT)



/* pltfm-specific */

#define ESDHC_HOST_CONTROL_LE	0x20



/*

 * eSDHC register definition

 */



/* Protocol Control Register */

#define ESDHC_PROCTL			0x28

#define ESDHC_CTRL_4BITBUS		(0x1 << 1)

#define ESDHC_CTRL_8BITBUS		(0x2 << 1)

#define ESDHC_CTRL_BUSWIDTH_MASK	(0x3 << 1)

#define ESDHC_HOST_CONTROL_RES		0x01



/* System Control Register */

#define ESDHC_SYSTEM_CONTROL		0x2c

#define ESDHC_CLOCK_MASK		0x0000fff0

#define ESDHC_PREDIV_SHIFT		8
@@ -34,20 +47,8 @@ 
#define ESDHC_CLOCK_HCKEN		0x00000002

#define ESDHC_CLOCK_IPGEN		0x00000001



/* pltfm-specific */

#define ESDHC_HOST_CONTROL_LE	0x20



/*

 * P2020 interpretation of the SDHCI_HOST_CONTROL register

 */

#define ESDHC_CTRL_4BITBUS          (0x1 << 1)

#define ESDHC_CTRL_8BITBUS          (0x2 << 1)

#define ESDHC_CTRL_BUSWIDTH_MASK    (0x3 << 1)



/* OF-specific */

/* Control Register for DMA transfer */

#define ESDHC_DMA_SYSCTL		0x40c

#define ESDHC_DMA_SNOOP			0x00000040



#define ESDHC_HOST_CONTROL_RES	0x01



#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */