Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a6634f83 authored by Alison Schofield's avatar Alison Schofield Committed by Greg Kroah-Hartman
Browse files

staging: iio: use kernel preferred block commenting style 



Use * on subsequent lines and trailing */ on a separate
line in block comments.

Signed-off-by: default avatarAlison Schofield <amsfield22@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 017168b5

drivers/staging/iio/adc/ad7192.c

+10 −10
Original line number Diff line number Diff line
@@ -35,10 +35,10 @@ 
#define AD7192_REG_DATA		3 /* Data Register	     (RO, 24/32-bit) */

#define AD7192_REG_ID		4 /* ID Register	     (RO, 8-bit) */

#define AD7192_REG_GPOCON	5 /* GPOCON Register	     (RO, 8-bit) */

#define AD7192_REG_OFFSET	6 /* Offset Register	     (RW, 16-bit

				   * (AD7792)/24-bit (AD7192)) */

#define AD7192_REG_FULLSALE	7 /* Full-Scale Register

				   * (RW, 16-bit (AD7792)/24-bit (AD7192)) */

#define AD7192_REG_OFFSET	6 /* Offset Register	     (RW, 16-bit */

				  /* (AD7792)/24-bit (AD7192)) */

#define AD7192_REG_FULLSALE	7 /* Full-Scale Register */

				  /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */



/* Communications Register Bit Designations (AD7192_REG_COMM) */

#define AD7192_COMM_WEN		BIT(7) /* Write Enable */
@@ -80,13 +80,13 @@ 
#define AD7192_MODE_CAL_SYS_FULL	7 /* System Full-Scale Calibration */



/* Mode Register: AD7192_MODE_CLKSRC options */

#define AD7192_CLK_EXT_MCLK1_2		0 /* External 4.92 MHz Clock connected

					   * from MCLK1 to MCLK2 */

#define AD7192_CLK_EXT_MCLK1_2		0 /* External 4.92 MHz Clock connected*/

					  /* from MCLK1 to MCLK2 */

#define AD7192_CLK_EXT_MCLK2		1 /* External Clock applied to MCLK2 */

#define AD7192_CLK_INT			2 /* Internal 4.92 MHz Clock not

					   * available at the MCLK2 pin */

#define AD7192_CLK_INT_CO		3 /* Internal 4.92 MHz Clock available

					   * at the MCLK2 pin */

#define AD7192_CLK_INT			2 /* Internal 4.92 MHz Clock not */

					  /* available at the MCLK2 pin */

#define AD7192_CLK_INT_CO		3 /* Internal 4.92 MHz Clock available*/

					  /* at the MCLK2 pin */



/* Configuration Register Bit Designations (AD7192_REG_CONF) */

drivers/staging/iio/impedance-analyzer/ad5933.c

+3 −2
Original line number Diff line number Diff line
@@ -691,8 +691,9 @@ static void ad5933_work(struct work_struct *work) 
	}



	if (status & AD5933_STAT_SWEEP_DONE) {

		/* last sample received - power down do nothing until

		 * the ring enable is toggled */

		/* last sample received - power down do

		 * nothing until the ring enable is toggled

		 */

		ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);

	} else {

		/* we just received a valid datum, move on to the next */

drivers/staging/iio/meter/ade7753.c

+2 −1
Original line number Diff line number Diff line
@@ -333,7 +333,8 @@ static int ade7753_set_irq(struct device *dev, bool enable) 


	if (enable)

		irqen |= BIT(3); /* Enables an interrupt when a data is

				    present in the waveform register */

				  * present in the waveform register

				  */

	else

		irqen &= ~BIT(3);

drivers/staging/iio/meter/ade7754.c

+2 −1
Original line number Diff line number Diff line
@@ -351,7 +351,8 @@ static int ade7754_set_irq(struct device *dev, bool enable) 


	if (enable)

		irqen |= BIT(14); /* Enables an interrupt when a data is

				     present in the waveform register */

				   * present in the waveform register

				   */

	else

		irqen &= ~BIT(14);

drivers/staging/iio/meter/ade7758_core.c

+2 −1
Original line number Diff line number Diff line
@@ -413,7 +413,8 @@ int ade7758_set_irq(struct device *dev, bool enable) 


	if (enable)

		irqen |= BIT(16); /* Enables an interrupt when a data is

				     present in the waveform register */

				   * present in the waveform register

				   */

	else

		irqen &= ~BIT(16);