Commit a63fcab4 authored Jan 24, 2013 by Stephane Eranian Committed by Arnaldo Carvalho de Melo Apr 01, 2013

perf/x86: Export PEBS load latency threshold register to sysfs



Make the PEBS Load Latency threshold register layout
and encoding visible to user level tools.

Signed-off-by: Stephane Eranian <eranian@google.com>
Cc: peterz@infradead.org
Cc: ak@linux.intel.com
Cc: acme@redhat.com
Cc: jolsa@redhat.com
Cc: namhyung.kim@lge.com
Link: http://lkml.kernel.org/r/1359040242-8269-10-git-send-email-eranian@google.com


Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

parent f20093ee

arch/x86/kernel/cpu/perf_event_intel.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -1781,6 +1781,8 @@ static void intel_pmu_flush_branch_stack(void)

		PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");

		PMU_FORMAT_ATTR(ldlat, "config1:0-15");

		static struct attribute *intel_arch3_formats_attr[] = {
		&format_attr_event.attr,
		&format_attr_umask.attr,
		@@ -1791,6 +1793,7 @@ static struct attribute *intel_arch3_formats_attr[] = {
		&format_attr_cmask.attr,

		&format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
		&format_attr_ldlat.attr, /* PEBS load latency */
		NULL,
		};