Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a63aaf5d authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: add mcp25xxfd support and DOC"

parents edc86e6f 1ec38c1e
Loading
Loading
Loading
Loading
+31 −0
Original line number Diff line number Diff line
* Microchip MCP2517 stand-alone CAN controller device tree bindings

Required properties:
 - compatible: Should be one of the following:
   - "microchip,mcp2517fd" for MCP2517fd.
 - reg: SPI chip select.
 - clocks: The clock feeding the CAN controller.
 - interrupt-parent: The parent interrupt controller.
 - interrupts: Should contain IRQ line for the CAN controller.
 - gpio-controller: Marks the device node as a GPIO controller

Optional properties:
 - vdd-supply: Regulator that powers the CAN controller.
 - xceiver-supply: Regulator that powers the CAN transceiver.
 - microchip,clock_out_div = <0|1|2|4|10>: Clock output pin divider
					   0 = Start of Frame output
					   default: 10
 - microchip,clock_div2: bool: divide the internal clock by 2
 - gpio_opendrain: bool: enable open-drain for all pins (except cantx)

Example:
	can0: can@1 {
		compatible = "microchip,mcp2517fd";
		reg = <1>;
		clocks = <&clk24m>;
		interrupt-parent = <&gpio4>;
		interrupts = <13 0x8>;
		vdd-supply = <&reg5v0>;
		xceiver-supply = <&reg5v0>;
		gpio-controller;
	};
+23 −0
Original line number Diff line number Diff line
@@ -107,3 +107,26 @@
		dr_mode = "host";
	};
};

&soc {
	clk40M: can_clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <40000000>;
	};
};

&qupv3_se0_spi {
	status = "okay";
	can@0 {
		compatible = "microchip,mcp2517fd";
		reg = <0>;
		clocks = <&clk40M>;
		interrupt-parent = <&tlmm>;
		interrupts = <15 0>;
		interrupt-names = "can_irq";
		spi-max-frequency = <10000000>;
		gpio-controller;
		status = "okay";
	};
};