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Commit a59781bb authored by Alex Deucher's avatar Alex Deucher
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drm/radeon: add support for interrupts on CIK (v5) 



Todo:
- handle interrupts for compute queues

v2: add documentation
v3: update to latest reset code
v4: update to latest illegal CP handling
v5: fix missing break in interrupt handler switch statement

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f6796cae

drivers/gpu/drm/radeon/cik.c

+840 −0

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/radeon/cikd.h

+170 −0
Original line number Diff line number Diff line
@@ -178,8 +178,42 @@ 
#define HDP_MISC_CNTL					0x2F4C

#define 	HDP_FLUSH_INVALIDATE_CACHE			(1 << 0)



#define IH_RB_CNTL                                        0x3e00

#       define IH_RB_ENABLE                               (1 << 0)

#       define IH_RB_SIZE(x)                              ((x) << 1) /* log2 */

#       define IH_RB_FULL_DRAIN_ENABLE                    (1 << 6)

#       define IH_WPTR_WRITEBACK_ENABLE                   (1 << 8)

#       define IH_WPTR_WRITEBACK_TIMER(x)                 ((x) << 9) /* log2 */

#       define IH_WPTR_OVERFLOW_ENABLE                    (1 << 16)

#       define IH_WPTR_OVERFLOW_CLEAR                     (1 << 31)

#define IH_RB_BASE                                        0x3e04

#define IH_RB_RPTR                                        0x3e08

#define IH_RB_WPTR                                        0x3e0c

#       define RB_OVERFLOW                                (1 << 0)

#       define WPTR_OFFSET_MASK                           0x3fffc

#define IH_RB_WPTR_ADDR_HI                                0x3e10

#define IH_RB_WPTR_ADDR_LO                                0x3e14

#define IH_CNTL                                           0x3e18

#       define ENABLE_INTR                                (1 << 0)

#       define IH_MC_SWAP(x)                              ((x) << 1)

#       define IH_MC_SWAP_NONE                            0

#       define IH_MC_SWAP_16BIT                           1

#       define IH_MC_SWAP_32BIT                           2

#       define IH_MC_SWAP_64BIT                           3

#       define RPTR_REARM                                 (1 << 4)

#       define MC_WRREQ_CREDIT(x)                         ((x) << 15)

#       define MC_WR_CLEAN_CNT(x)                         ((x) << 20)

#       define MC_VMID(x)                                 ((x) << 25)



#define	CONFIG_MEMSIZE					0x5428



#define INTERRUPT_CNTL                                    0x5468

#       define IH_DUMMY_RD_OVERRIDE                       (1 << 0)

#       define IH_DUMMY_RD_EN                             (1 << 1)

#       define IH_REQ_NONSNOOP_EN                         (1 << 3)

#       define GEN_IH_INT_EN                              (1 << 8)

#define INTERRUPT_CNTL2                                   0x546c



#define HDP_MEM_COHERENCY_FLUSH_CNTL			0x5480



#define	BIF_FB_EN						0x5490
@@ -203,6 +237,99 @@ 
#define		SDMA0					(1 << 10)

#define		SDMA1					(1 << 11)



/* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */

#define LB_VLINE_STATUS                                 0x6b24

#       define VLINE_OCCURRED                           (1 << 0)

#       define VLINE_ACK                                (1 << 4)

#       define VLINE_STAT                               (1 << 12)

#       define VLINE_INTERRUPT                          (1 << 16)

#       define VLINE_INTERRUPT_TYPE                     (1 << 17)

/* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */

#define LB_VBLANK_STATUS                                0x6b2c

#       define VBLANK_OCCURRED                          (1 << 0)

#       define VBLANK_ACK                               (1 << 4)

#       define VBLANK_STAT                              (1 << 12)

#       define VBLANK_INTERRUPT                         (1 << 16)

#       define VBLANK_INTERRUPT_TYPE                    (1 << 17)



/* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */

#define LB_INTERRUPT_MASK                               0x6b20

#       define VBLANK_INTERRUPT_MASK                    (1 << 0)

#       define VLINE_INTERRUPT_MASK                     (1 << 4)

#       define VLINE2_INTERRUPT_MASK                    (1 << 8)



#define DISP_INTERRUPT_STATUS                           0x60f4

#       define LB_D1_VLINE_INTERRUPT                    (1 << 2)

#       define LB_D1_VBLANK_INTERRUPT                   (1 << 3)

#       define DC_HPD1_INTERRUPT                        (1 << 17)

#       define DC_HPD1_RX_INTERRUPT                     (1 << 18)

#       define DACA_AUTODETECT_INTERRUPT                (1 << 22)

#       define DACB_AUTODETECT_INTERRUPT                (1 << 23)

#       define DC_I2C_SW_DONE_INTERRUPT                 (1 << 24)

#       define DC_I2C_HW_DONE_INTERRUPT                 (1 << 25)

#define DISP_INTERRUPT_STATUS_CONTINUE                  0x60f8

#       define LB_D2_VLINE_INTERRUPT                    (1 << 2)

#       define LB_D2_VBLANK_INTERRUPT                   (1 << 3)

#       define DC_HPD2_INTERRUPT                        (1 << 17)

#       define DC_HPD2_RX_INTERRUPT                     (1 << 18)

#       define DISP_TIMER_INTERRUPT                     (1 << 24)

#define DISP_INTERRUPT_STATUS_CONTINUE2                 0x60fc

#       define LB_D3_VLINE_INTERRUPT                    (1 << 2)

#       define LB_D3_VBLANK_INTERRUPT                   (1 << 3)

#       define DC_HPD3_INTERRUPT                        (1 << 17)

#       define DC_HPD3_RX_INTERRUPT                     (1 << 18)

#define DISP_INTERRUPT_STATUS_CONTINUE3                 0x6100

#       define LB_D4_VLINE_INTERRUPT                    (1 << 2)

#       define LB_D4_VBLANK_INTERRUPT                   (1 << 3)

#       define DC_HPD4_INTERRUPT                        (1 << 17)

#       define DC_HPD4_RX_INTERRUPT                     (1 << 18)

#define DISP_INTERRUPT_STATUS_CONTINUE4                 0x614c

#       define LB_D5_VLINE_INTERRUPT                    (1 << 2)

#       define LB_D5_VBLANK_INTERRUPT                   (1 << 3)

#       define DC_HPD5_INTERRUPT                        (1 << 17)

#       define DC_HPD5_RX_INTERRUPT                     (1 << 18)

#define DISP_INTERRUPT_STATUS_CONTINUE5                 0x6150

#       define LB_D6_VLINE_INTERRUPT                    (1 << 2)

#       define LB_D6_VBLANK_INTERRUPT                   (1 << 3)

#       define DC_HPD6_INTERRUPT                        (1 << 17)

#       define DC_HPD6_RX_INTERRUPT                     (1 << 18)

#define DISP_INTERRUPT_STATUS_CONTINUE6                 0x6780



#define	DAC_AUTODETECT_INT_CONTROL			0x67c8



#define DC_HPD1_INT_STATUS                              0x601c

#define DC_HPD2_INT_STATUS                              0x6028

#define DC_HPD3_INT_STATUS                              0x6034

#define DC_HPD4_INT_STATUS                              0x6040

#define DC_HPD5_INT_STATUS                              0x604c

#define DC_HPD6_INT_STATUS                              0x6058

#       define DC_HPDx_INT_STATUS                       (1 << 0)

#       define DC_HPDx_SENSE                            (1 << 1)

#       define DC_HPDx_SENSE_DELAYED                    (1 << 4)

#       define DC_HPDx_RX_INT_STATUS                    (1 << 8)



#define DC_HPD1_INT_CONTROL                             0x6020

#define DC_HPD2_INT_CONTROL                             0x602c

#define DC_HPD3_INT_CONTROL                             0x6038

#define DC_HPD4_INT_CONTROL                             0x6044

#define DC_HPD5_INT_CONTROL                             0x6050

#define DC_HPD6_INT_CONTROL                             0x605c

#       define DC_HPDx_INT_ACK                          (1 << 0)

#       define DC_HPDx_INT_POLARITY                     (1 << 8)

#       define DC_HPDx_INT_EN                           (1 << 16)

#       define DC_HPDx_RX_INT_ACK                       (1 << 20)

#       define DC_HPDx_RX_INT_EN                        (1 << 24)



#define DC_HPD1_CONTROL                                   0x6024

#define DC_HPD2_CONTROL                                   0x6030

#define DC_HPD3_CONTROL                                   0x603c

#define DC_HPD4_CONTROL                                   0x6048

#define DC_HPD5_CONTROL                                   0x6054

#define DC_HPD6_CONTROL                                   0x6060

#       define DC_HPDx_CONNECTION_TIMER(x)                ((x) << 0)

#       define DC_HPDx_RX_INT_TIMER(x)                    ((x) << 16)

#       define DC_HPDx_EN                                 (1 << 28)



#define	GRBM_CNTL					0x8000

#define		GRBM_READ_TIMEOUT(x)				((x) << 0)
@@ -274,6 +401,10 @@ 
#define		SOFT_RESET_CPC					(1 << 18) /* CP Compute (MEC1/2) */

#define		SOFT_RESET_CPG					(1 << 19) /* CP GFX (PFP, ME, CE) */



#define GRBM_INT_CNTL                                   0x8060

#       define RDERR_INT_ENABLE                         (1 << 0)

#       define GUI_IDLE_INT_ENABLE                      (1 << 19)



#define CP_MEC_CNTL					0x8234

#define		MEC_ME2_HALT					(1 << 28)

#define		MEC_ME1_HALT					(1 << 30)
@@ -507,6 +638,45 @@ 
#       define CP_RINGID1_INT_ENABLE                    (1 << 30)

#       define CP_RINGID0_INT_ENABLE                    (1 << 31)



#define CP_INT_STATUS_RING0                             0xC1B4

#       define PRIV_INSTR_INT_STAT                      (1 << 22)

#       define PRIV_REG_INT_STAT                        (1 << 23)

#       define TIME_STAMP_INT_STAT                      (1 << 26)

#       define CP_RINGID2_INT_STAT                      (1 << 29)

#       define CP_RINGID1_INT_STAT                      (1 << 30)

#       define CP_RINGID0_INT_STAT                      (1 << 31)



#define CP_ME1_PIPE0_INT_CNTL                           0xC214

#define CP_ME1_PIPE1_INT_CNTL                           0xC218

#define CP_ME1_PIPE2_INT_CNTL                           0xC21C

#define CP_ME1_PIPE3_INT_CNTL                           0xC220

#define CP_ME2_PIPE0_INT_CNTL                           0xC224

#define CP_ME2_PIPE1_INT_CNTL                           0xC228

#define CP_ME2_PIPE2_INT_CNTL                           0xC22C

#define CP_ME2_PIPE3_INT_CNTL                           0xC230

#       define DEQUEUE_REQUEST_INT_ENABLE               (1 << 13)

#       define WRM_POLL_TIMEOUT_INT_ENABLE              (1 << 17)

#       define PRIV_REG_INT_ENABLE                      (1 << 23)

#       define TIME_STAMP_INT_ENABLE                    (1 << 26)

#       define GENERIC2_INT_ENABLE                      (1 << 29)

#       define GENERIC1_INT_ENABLE                      (1 << 30)

#       define GENERIC0_INT_ENABLE                      (1 << 31)

#define CP_ME1_PIPE0_INT_STATUS                         0xC214

#define CP_ME1_PIPE1_INT_STATUS                         0xC218

#define CP_ME1_PIPE2_INT_STATUS                         0xC21C

#define CP_ME1_PIPE3_INT_STATUS                         0xC220

#define CP_ME2_PIPE0_INT_STATUS                         0xC224

#define CP_ME2_PIPE1_INT_STATUS                         0xC228

#define CP_ME2_PIPE2_INT_STATUS                         0xC22C

#define CP_ME2_PIPE3_INT_STATUS                         0xC230

#       define DEQUEUE_REQUEST_INT_STATUS               (1 << 13)

#       define WRM_POLL_TIMEOUT_INT_STATUS              (1 << 17)

#       define PRIV_REG_INT_STATUS                      (1 << 23)

#       define TIME_STAMP_INT_STATUS                    (1 << 26)

#       define GENERIC2_INT_STATUS                      (1 << 29)

#       define GENERIC1_INT_STATUS                      (1 << 30)

#       define GENERIC0_INT_STATUS                      (1 << 31)



#define	CP_MAX_CONTEXT					0xC2B8



#define	CP_RB0_BASE_HI					0xC2C4

drivers/gpu/drm/radeon/radeon.h

+11 −0
Original line number Diff line number Diff line
@@ -600,10 +600,21 @@ struct evergreen_irq_stat_regs { 
	u32 afmt_status6;

};



struct cik_irq_stat_regs {

	u32 disp_int;

	u32 disp_int_cont;

	u32 disp_int_cont2;

	u32 disp_int_cont3;

	u32 disp_int_cont4;

	u32 disp_int_cont5;

	u32 disp_int_cont6;

};



union radeon_irq_stat_regs {

	struct r500_irq_stat_regs r500;

	struct r600_irq_stat_regs r600;

	struct evergreen_irq_stat_regs evergreen;

	struct cik_irq_stat_regs cik;

};



#define RADEON_MAX_HPD_PINS 6