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Commit a58b5acc authored by Chetan C R's avatar Chetan C R Committed by Gerrit - the friendly Code Review server
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clk: qcom: gcc: Update the halt flags for clocks on SDM660 



The UFS tx/rx clocks are dependent on the external sources
to be enabled, thus skip polling for the CLK_OFF bit.
Update the halt flag for these UFS clocks to halt skip.
Also at the same time update similar dependent clocks halt flags.

Change-Id: I7e6cfd3a3fa22f2505f45d42abc5477a2dad30bf
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
Signed-off-by: default avatarChetan C R <cchinnad@codeaurora.org>
parent 95c7bdc8

drivers/clk/qcom/gcc-sdm660.c

+4 −4
Original line number Diff line number Diff line
@@ -1750,7 +1750,7 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = { 


static struct clk_branch gpll0_out_msscc = {

	.halt_reg = 0x5200c,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x5200c,

		.enable_mask = BIT(2),
@@ -2249,7 +2249,7 @@ static struct clk_branch gcc_ufs_phy_aux_hw_ctl_clk = { 


static struct clk_branch gcc_ufs_rx_symbol_0_clk = {

	.halt_reg = 0x75014,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x75014,

		.enable_mask = BIT(0),
@@ -2262,7 +2262,7 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = { 


static struct clk_branch gcc_ufs_rx_symbol_1_clk = {

	.halt_reg = 0x7605c,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x7605c,

		.enable_mask = BIT(0),
@@ -2275,7 +2275,7 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = { 


static struct clk_branch gcc_ufs_tx_symbol_0_clk = {

	.halt_reg = 0x75010,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x75010,

		.enable_mask = BIT(0),