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Commit a518d637 authored by Alexey Brodkin's avatar Alexey Brodkin Committed by Vineet Gupta
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ARC: [plat-hsdk] initial port for HSDK board 



This initial port adds support of ARC HS Development Kit board with some
basic features such serial port, USB, SD/MMC and Ethernet.

Essentially we run Linux kernel on all 4 cores (i.e. utilize SMP) and
heavily use IO Coherency for speeding-up DMA-aware peripherals.

Note as opposed to other ARC boards we link Linux kernel to
0x9000_0000 intentionally because cores 1 and 3 configured with DCCM
situated at our more usual link base 0x8000_0000. We still can use
memory region starting at 0x8000_0000 as we reallocate DCCM in our
platform code.

Note that PAE remapping for DMA clients does not work due to an RTL bug,
so CREG_PAE register must be programmed to all zeroes, otherwise it will
cause problems with DMA to/from peripherals even if PAE40 is not used.

Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarAlexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: default avatarEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent 9ed68785

Documentation/devicetree/bindings/arc/hsdk.txt

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Synopsys DesignWare ARC HS Development Kit Device Tree Bindings

---------------------------------------------------------------------------



ARC HSDK Board with quad-core ARC HS38x4 in silicon.



Required root node properties:

    - compatible = "snps,hsdk";

arch/arc/Kconfig

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@@ -100,6 +100,7 @@ source "arch/arc/plat-tb10x/Kconfig" 
source "arch/arc/plat-axs10x/Kconfig"

#New platform adds here

source "arch/arc/plat-eznps/Kconfig"

source "arch/arc/plat-hsdk/Kconfig"



endmenu

arch/arc/Makefile

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@@ -111,6 +111,7 @@ core-y += arch/arc/plat-sim/ 
core-$(CONFIG_ARC_PLAT_TB10X)	+= arch/arc/plat-tb10x/

core-$(CONFIG_ARC_PLAT_AXS10X)	+= arch/arc/plat-axs10x/

core-$(CONFIG_ARC_PLAT_EZNPS)	+= arch/arc/plat-eznps/

core-$(CONFIG_ARC_SOC_HSDK)	+= arch/arc/plat-hsdk/



ifdef CONFIG_ARC_PLAT_EZNPS

KBUILD_CPPFLAGS += -I$(srctree)/arch/arc/plat-eznps/include

arch/arc/boot/dts/hsdk.dts

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/*

 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



/*

 * Device Tree for ARC HS Development Kit

 */

/dts-v1/;



#include <dt-bindings/net/ti-dp83867.h>



/ {

	model = "snps,hsdk";

	compatible = "snps,hsdk";



	#address-cells = <1>;

	#size-cells = <1>;



	chosen {

		bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			device_type = "cpu";

			compatible = "snps,archs38";

			reg = <0>;

			clocks = <&core_clk>;

		};



		cpu@1 {

			device_type = "cpu";

			compatible = "snps,archs38";

			reg = <1>;

			clocks = <&core_clk>;

		};



		cpu@2 {

			device_type = "cpu";

			compatible = "snps,archs38";

			reg = <2>;

			clocks = <&core_clk>;

		};



		cpu@3 {

			device_type = "cpu";

			compatible = "snps,archs38";

			reg = <3>;

			clocks = <&core_clk>;

		};

	};



	core_clk: core-clk {

		#clock-cells = <0>;

		compatible = "fixed-clock";

		clock-frequency = <500000000>;

	};



	cpu_intc: cpu-interrupt-controller {

		compatible = "snps,archs-intc";

		interrupt-controller;

		#interrupt-cells = <1>;

	};



	idu_intc: idu-interrupt-controller {

		compatible = "snps,archs-idu-intc";

		interrupt-controller;

		#interrupt-cells = <1>;

		interrupt-parent = <&cpu_intc>;

	};



	arcpct: pct {

		compatible = "snps,archs-pct";

	};



	/* TIMER0 with interrupt for clockevent */

	timer {

		compatible = "snps,arc-timer";

		interrupts = <16>;

		interrupt-parent = <&cpu_intc>;

		clocks = <&core_clk>;

	};



	/* 64-bit Global Free Running Counter */

	gfrc {

		compatible = "snps,archs-timer-gfrc";

		clocks = <&core_clk>;

	};



	soc {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		interrupt-parent = <&idu_intc>;



		ranges = <0x00000000 0xf0000000 0x10000000>;



		serial: serial@5000 {

			compatible = "snps,dw-apb-uart";

			reg = <0x5000 0x100>;

			clock-frequency = <33330000>;

			interrupts = <6>;

			baud = <115200>;

			reg-shift = <2>;

			reg-io-width = <4>;

		};



		gmacclk: gmacclk {

			compatible = "fixed-clock";

			clock-frequency = <400000000>;

			#clock-cells = <0>;

		};



		mmcclk_ciu: mmcclk-ciu {

			compatible = "fixed-clock";

			clock-frequency = <100000000>;

			#clock-cells = <0>;

		};



		mmcclk_biu: mmcclk-biu {

			compatible = "fixed-clock";

			clock-frequency = <400000000>;

			#clock-cells = <0>;

		};



		ethernet@8000 {

			#interrupt-cells = <1>;

			compatible = "snps,dwmac";

			reg = <0x8000 0x2000>;

			interrupts = <10>;

			interrupt-names = "macirq";

			phy-mode = "rgmii";

			snps,pbl = <32>;

			clocks = <&gmacclk>;

			clock-names = "stmmaceth";

			phy-handle = <&phy0>;



			mdio {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "snps,dwmac-mdio";

				phy0: ethernet-phy@0 {

					reg = <0>;

					ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;

					ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;

					ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

				};

			};

		};



		ohci@60000 {

			compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";

			reg = <0x60000 0x100>;

			interrupts = <15>;

		};



		ehci@40000 {

			compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";

			reg = <0x40000 0x100>;

			interrupts = <15>;

		};



		mmc@a000 {

			compatible = "altr,socfpga-dw-mshc";

			reg = <0xa000 0x400>;

			num-slots = <1>;

			fifo-depth = <16>;

			card-detect-delay = <200>;

			clocks = <&mmcclk_biu>, <&mmcclk_ciu>;

			clock-names = "biu", "ciu";

			interrupts = <12>;

			bus-width = <4>;

		};

	};



	memory@80000000 {

		#address-cells = <1>;

		#size-cells = <1>;

		device_type = "memory";

		reg = <0x80000000 0x40000000>;  /* 1 GiB */

	};

};

arch/arc/configs/hsdk_defconfig

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CONFIG_DEFAULT_HOSTNAME="ARCLinux"

CONFIG_SYSVIPC=y

# CONFIG_CROSS_MEMORY_ATTACH is not set

CONFIG_NO_HZ_IDLE=y

CONFIG_HIGH_RES_TIMERS=y

CONFIG_IKCONFIG=y

CONFIG_IKCONFIG_PROC=y

CONFIG_NAMESPACES=y

# CONFIG_UTS_NS is not set

# CONFIG_PID_NS is not set

CONFIG_BLK_DEV_INITRD=y

CONFIG_INITRAMFS_SOURCE="../../arc_initramfs_hs/"

CONFIG_EMBEDDED=y

CONFIG_PERF_EVENTS=y

# CONFIG_VM_EVENT_COUNTERS is not set

# CONFIG_COMPAT_BRK is not set

CONFIG_SLAB=y

CONFIG_MODULES=y

CONFIG_MODULE_UNLOAD=y

CONFIG_ARC_SOC_HSDK=y

CONFIG_ISA_ARCV2=y

CONFIG_SMP=y

CONFIG_LINUX_LINK_BASE=0x90000000

CONFIG_LINUX_RAM_BASE=0x80000000

CONFIG_ARC_BUILTIN_DTB_NAME="hsdk"

CONFIG_PREEMPT=y

# CONFIG_COMPACTION is not set

CONFIG_NET=y

CONFIG_PACKET=y

CONFIG_UNIX=y

CONFIG_INET=y

CONFIG_DEVTMPFS=y

# CONFIG_STANDALONE is not set

# CONFIG_PREVENT_FIRMWARE_BUILD is not set

# CONFIG_FIRMWARE_IN_KERNEL is not set

CONFIG_SCSI=y

CONFIG_BLK_DEV_SD=y

CONFIG_NETDEVICES=y

CONFIG_STMMAC_ETH=y

CONFIG_MICREL_PHY=y

CONFIG_INPUT_EVDEV=y

# CONFIG_INPUT_KEYBOARD is not set

# CONFIG_INPUT_MOUSE is not set

# CONFIG_SERIO is not set

# CONFIG_LEGACY_PTYS is not set

CONFIG_SERIAL_8250=y

CONFIG_SERIAL_8250_CONSOLE=y

CONFIG_SERIAL_8250_DW=y

CONFIG_SERIAL_OF_PLATFORM=y

# CONFIG_HW_RANDOM is not set

# CONFIG_HWMON is not set

CONFIG_FB=y

CONFIG_FB_UDL=y

CONFIG_FRAMEBUFFER_CONSOLE=y

CONFIG_USB=y

CONFIG_USB_EHCI_HCD=y

CONFIG_USB_EHCI_HCD_PLATFORM=y

CONFIG_USB_OHCI_HCD=y

CONFIG_USB_OHCI_HCD_PLATFORM=y

CONFIG_USB_STORAGE=y

CONFIG_MMC=y

CONFIG_MMC_SDHCI=y

CONFIG_MMC_SDHCI_PLTFM=y

CONFIG_MMC_DW=y

# CONFIG_IOMMU_SUPPORT is not set

CONFIG_EXT3_FS=y

CONFIG_VFAT_FS=y

CONFIG_TMPFS=y

CONFIG_NFS_FS=y

CONFIG_NLS_CODEPAGE_437=y

CONFIG_NLS_ISO8859_1=y

# CONFIG_ENABLE_WARN_DEPRECATED is not set

# CONFIG_ENABLE_MUST_CHECK is not set

CONFIG_STRIP_ASM_SYMS=y

CONFIG_LOCKUP_DETECTOR=y

CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10

# CONFIG_SCHED_DEBUG is not set

# CONFIG_DEBUG_PREEMPT is not set

# CONFIG_FTRACE is not set

CONFIG_CRYPTO_ECHAINIV=y