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Commit a4713c5a authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

drm/i915/cnl: Add Wa_2201832410 



"Clock gating bug in GWL may not clear barrier state when an EOT
is received, causing a hang the next time that barrier is used."

HSDES: 2201832410

Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarRafael Antognolli <rafael.antognolli@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180307220912.3681-1-rodrigo.vivi@intel.com
parent a89a70a8

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -3965,6 +3965,9 @@ enum { 
#define  SARBUNIT_CLKGATE_DIS		(1 << 5)

#define  RCCUNIT_CLKGATE_DIS		(1 << 7)



#define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)

#define  GWUNIT_CLKGATE_DIS		(1 << 16)



#define UNSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9434)

#define  VFUNIT_CLKGATE_DIS		(1 << 20)

drivers/gpu/drm/i915/intel_pm.c

+5 −0
Original line number Diff line number Diff line
@@ -8522,6 +8522,11 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv) 
		val |= SARBUNIT_CLKGATE_DIS;

	I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);



	/* Wa_2201832410:cnl */

	val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);

	val |= GWUNIT_CLKGATE_DIS;

	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);



	/* WaDisableVFclkgate:cnl */

	/* WaVFUnitClockGatingDisable:cnl */

	val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);