Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a44628b9 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Clean up LVDS pipe select bits 



Clean up the LVDS pipe select bits. To make the whole situation a bit
less ugly we'll start to share the same code between .get_hw_state()
and the port state asserts.

v2: Order the defines shift,mask,value (Jani)
    Drop ruperfluous braces and whitesapce changes (Jani)
    Combine masks in compute_is_dual_link_lvds() (Jani)
v3: Fix LVDS_PIPE_SEL_MASK_CPT

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180514182827.28629-1-ville.syrjala@linux.intel.com
parent 6102a8ee

drivers/gpu/drm/i915/i915_reg.h

+6 −3
Original line number Diff line number Diff line
@@ -4392,9 +4392,12 @@ enum { 
 */

#define   LVDS_PORT_EN			(1 << 31)

/* Selects pipe B for LVDS data.  Must be set on pre-965. */

#define   LVDS_PIPEB_SELECT		(1 << 30)

#define   LVDS_PIPE_MASK		(1 << 30)

#define   LVDS_PIPE(pipe)		((pipe) << 30)

#define   LVDS_PIPE_SEL_SHIFT		30

#define   LVDS_PIPE_SEL_MASK		(1 << 30)

#define   LVDS_PIPE_SEL(pipe)		((pipe) << 30)

#define   LVDS_PIPE_SEL_SHIFT_CPT	29

#define   LVDS_PIPE_SEL_MASK_CPT	(3 << 29)

#define   LVDS_PIPE_SEL_CPT(pipe)	((pipe) << 29)

/* LVDS dithering flag on 965/g4x platform */

#define   LVDS_ENABLE_DITHER		(1 << 25)

/* LVDS sync polarity flags. Set to invert (i.e. negative) */

drivers/gpu/drm/i915/intel_display.c

+7 −26
Original line number Diff line number Diff line
@@ -1214,9 +1214,8 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) 
		pp_reg = PP_CONTROL(0);

		port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;



		if (port_sel == PANEL_PORT_SELECT_LVDS &&

		    I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)

			panel_pipe = PIPE_B;

		if (port_sel == PANEL_PORT_SELECT_LVDS)

			intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);

		/* XXX: else fix for eDP */

	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		/* presumably write lock depends on pipe, not port select */
@@ -1224,8 +1223,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) 
		panel_pipe = pipe;

	} else {

		pp_reg = PP_CONTROL(0);

		if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)

			panel_pipe = PIPE_B;

		intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);

	}



	val = I915_READ(pp_reg);
@@ -1344,22 +1342,6 @@ static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, 
	return true;

}



static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,

			      enum pipe pipe, u32 val)

{

	if ((val & LVDS_PORT_EN) == 0)

		return false;



	if (HAS_PCH_CPT(dev_priv)) {

		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))

			return false;

	} else {

		if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))

			return false;

	}

	return true;

}



static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,

				   enum pipe pipe, i915_reg_t reg,

				   u32 port_sel)
@@ -1391,7 +1373,6 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 
				      enum pipe pipe)

{

	enum pipe port_pipe;

	u32 val;



	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);

	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
@@ -1402,8 +1383,8 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 
			"PCH VGA enabled on transcoder %c, should be disabled\n",

			pipe_name(pipe));



	val = I915_READ(PCH_LVDS);

	I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),

	I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&

			port_pipe == pipe,

			"PCH LVDS enabled on transcoder %c, should be disabled\n",

			pipe_name(pipe));

drivers/gpu/drm/i915/intel_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -1824,6 +1824,8 @@ void intel_infoframe_init(struct intel_digital_port *intel_dig_port); 




/* intel_lvds.c */

bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,

			     i915_reg_t lvds_reg, enum pipe *pipe);

void intel_lvds_init(struct drm_i915_private *dev_priv);

struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);

bool intel_is_dual_link_lvds(struct drm_device *dev);

drivers/gpu/drm/i915/intel_lvds.c

+27 −25
Original line number Diff line number Diff line
@@ -85,34 +85,35 @@ static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *conn 
	return container_of(connector, struct intel_lvds_connector, base.base);

}



bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,

			     i915_reg_t lvds_reg, enum pipe *pipe)

{

	u32 val;



	val = I915_READ(lvds_reg);



	/* asserts want to know the pipe even if the port is disabled */

	if (HAS_PCH_CPT(dev_priv))

		*pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT;

	else

		*pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT;



	return val & LVDS_PORT_EN;

}



static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,

				    enum pipe *pipe)

{

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);

	u32 tmp;

	bool ret;



	if (!intel_display_power_get_if_enabled(dev_priv,

						encoder->power_domain))

		return false;



	ret = false;

	ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe);



	tmp = I915_READ(lvds_encoder->reg);



	if (!(tmp & LVDS_PORT_EN))

		goto out;



	if (HAS_PCH_CPT(dev_priv))

		*pipe = PORT_TO_PIPE_CPT(tmp);

	else

		*pipe = PORT_TO_PIPE(tmp);



	ret = true;



out:

	intel_display_power_put(dev_priv, encoder->power_domain);



	return ret;
@@ -255,14 +256,11 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder, 
	temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;



	if (HAS_PCH_CPT(dev_priv)) {

		temp &= ~PORT_TRANS_SEL_MASK;

		temp |= PORT_TRANS_SEL_CPT(pipe);

	} else {

		if (pipe == 1) {

			temp |= LVDS_PIPEB_SELECT;

		temp &= ~LVDS_PIPE_SEL_MASK_CPT;

		temp |= LVDS_PIPE_SEL_CPT(pipe);

	} else {

			temp &= ~LVDS_PIPEB_SELECT;

		}

		temp &= ~LVDS_PIPE_SEL_MASK;

		temp |= LVDS_PIPE_SEL(pipe);

	}



	/* set the corresponsding LVDS_BORDER bit */
@@ -908,7 +906,11 @@ static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) 
	 * register is uninitialized.

	 */

	val = I915_READ(lvds_encoder->reg);

	if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))

	if (HAS_PCH_CPT(dev_priv))

		val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);

	else

		val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);

	if (val == 0)

		val = dev_priv->vbt.bios_lvds_val;



	return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;