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Commit a4386450 authored by Jeeja KP's avatar Jeeja KP Committed by Mark Brown
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ASoC: Intel: Skylake: Clear stream registers before stream setup 



This patch adds clean up routine to clear the stream registers and
calls this routine before setting up stream registers.

Signed-off-by: default avatarJeeja KP <jeeja.kp@intel.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 743ad80e

sound/soc/intel/skylake/skl-sst-cldma.c

+23 −15
Original line number Diff line number Diff line
@@ -60,6 +60,27 @@ static void skl_cldma_stream_run(struct sst_dsp *ctx, bool enable) 
		dev_err(ctx->dev, "Failed to set Run bit=%d enable=%d\n", val, enable);

}



static void skl_cldma_stream_clear(struct sst_dsp  *ctx)

{

	/* make sure Run bit is cleared before setting stream register */

	skl_cldma_stream_run(ctx, 0);



	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,

				CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(0));

	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,

				CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(0));

	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,

				CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(0));

	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,

				CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(0));



	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0));

	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0);



	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0);

	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0);

}



/* Code loader helper APIs */

static void skl_cldma_setup_bdle(struct sst_dsp *ctx,

		struct snd_dma_buffer *dmab_data,
@@ -95,6 +116,7 @@ static void skl_cldma_setup_controller(struct sst_dsp *ctx, 
		struct snd_dma_buffer *dmab_bdl, unsigned int max_size,

		u32 count)

{

	skl_cldma_stream_clear(ctx);

	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL,

			CL_SD_BDLPLBA(dmab_bdl->addr));

	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU,
@@ -137,21 +159,7 @@ static void skl_cldma_cleanup_spb(struct sst_dsp *ctx) 
static void skl_cldma_cleanup(struct sst_dsp  *ctx)

{

	skl_cldma_cleanup_spb(ctx);



	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,

				CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(0));

	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,

				CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(0));

	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,

				CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(0));

	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,

				CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(0));



	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0));

	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0);



	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0);

	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0);

	skl_cldma_stream_clear(ctx);



	ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);

	ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_bdl);