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Commit a413647b authored by Mike Frysinger's avatar Mike Frysinger
Browse files

Blackfin: pull updated anomaly lists from toolchain 



Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent 648882d9

arch/blackfin/mach-bf518/include/mach/anomaly.h

+32 −3
Original line number Diff line number Diff line
@@ -6,14 +6,19 @@ 
 * Licensed under the GPL-2 or later.

 */



/* This file shoule be up to date with:

/* This file should be up to date with:

 *  - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List

 */



/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */

#if __SILICON_REVISION__ < 0

# error will not work on BF518 silicon version

#endif



#ifndef _MACH_ANOMALY_H_

#define _MACH_ANOMALY_H_



/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */

/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */

#define ANOMALY_05000074 (1)

/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */

#define ANOMALY_05000122 (1)
@@ -47,7 +52,7 @@ 
#define ANOMALY_05000435 (1)

/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */

#define ANOMALY_05000438 (1)

/* Preboot Cannot be Used to Program the PLL_DIV Register */

/* Preboot Cannot be Used to Alter the PLL_DIV Register */

#define ANOMALY_05000439 (1)

/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */

#define ANOMALY_05000440 (1)
@@ -61,32 +66,56 @@ 
#define ANOMALY_05000453 (1)

/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */

#define ANOMALY_05000455 (1)

/* False Hardware Error when RETI points to invalid memory */

#define ANOMALY_05000461 (1)



/* Anomalies that don't exist on this proc */

#define ANOMALY_05000099 (0)

#define ANOMALY_05000119 (0)

#define ANOMALY_05000120 (0)

#define ANOMALY_05000125 (0)

#define ANOMALY_05000149 (0)

#define ANOMALY_05000158 (0)

#define ANOMALY_05000171 (0)

#define ANOMALY_05000179 (0)

#define ANOMALY_05000183 (0)

#define ANOMALY_05000198 (0)

#define ANOMALY_05000215 (0)

#define ANOMALY_05000220 (0)

#define ANOMALY_05000227 (0)

#define ANOMALY_05000230 (0)

#define ANOMALY_05000231 (0)

#define ANOMALY_05000233 (0)

#define ANOMALY_05000242 (0)

#define ANOMALY_05000244 (0)

#define ANOMALY_05000248 (0)

#define ANOMALY_05000250 (0)

#define ANOMALY_05000261 (0)

#define ANOMALY_05000263 (0)

#define ANOMALY_05000266 (0)

#define ANOMALY_05000273 (0)

#define ANOMALY_05000274 (0)

#define ANOMALY_05000278 (0)

#define ANOMALY_05000285 (0)

#define ANOMALY_05000287 (0)

#define ANOMALY_05000301 (0)

#define ANOMALY_05000305 (0)

#define ANOMALY_05000307 (0)

#define ANOMALY_05000311 (0)

#define ANOMALY_05000312 (0)

#define ANOMALY_05000323 (0)

#define ANOMALY_05000353 (0)

#define ANOMALY_05000362 (1)

#define ANOMALY_05000363 (0)

#define ANOMALY_05000380 (0)

#define ANOMALY_05000386 (0)

#define ANOMALY_05000389 (0)

#define ANOMALY_05000400 (0)

#define ANOMALY_05000412 (0)

#define ANOMALY_05000432 (0)

#define ANOMALY_05000447 (0)

#define ANOMALY_05000448 (0)

#define ANOMALY_05000456 (0)

#define ANOMALY_05000450 (0)



#endif

arch/blackfin/mach-bf527/include/mach/anomaly.h

+109 −59
Original line number Diff line number Diff line
@@ -6,14 +6,19 @@ 
 * Licensed under the GPL-2 or later.

 */



/* This file shoule be up to date with:

 *  - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List

 *  - Revision E, 08/18/2008; ADSP-BF527 Blackfin Processor Anomaly List

/* This file should be up to date with:

 *  - Revision C, 03/13/2009; ADSP-BF526 Blackfin Processor Anomaly List

 *  - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List

 */



#ifndef _MACH_ANOMALY_H_

#define _MACH_ANOMALY_H_



/* We do not support old silicon - sorry */

#if __SILICON_REVISION__ < 0

# error will not work on BF526/BF527 silicon version

#endif



#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)

# define ANOMALY_BF526 1

#else
@@ -25,158 +30,203 @@ 
# define ANOMALY_BF527 0

#endif



/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */

#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526)

#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)

#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))



/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */

#define ANOMALY_05000074 (1)

/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */

#define ANOMALY_05000119 (1)	/* note: brokenness is noted in documentation, not anomaly sheet */

/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */

#define ANOMALY_05000122 (1)

/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */

/* False Hardware Error from an Access in the Shadow of a Conditional Branch */

#define ANOMALY_05000245 (1)

/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */

#define ANOMALY_05000254 (1)

/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */

#define ANOMALY_05000265 (1)

/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */

#define ANOMALY_05000310 (1)

/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */

#define ANOMALY_05000313 (__SILICON_REVISION__ < 2)

#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2))

/* Incorrect Access of OTP_STATUS During otp_write() Function */

#define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))

/* Host DMA Boot Modes Are Not Functional */

#define ANOMALY_05000330 (__SILICON_REVISION__ < 2)

/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */

#define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))

/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */

#define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000341 (_ANOMALY_BF527(< 2))

/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */

#define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000342 (_ANOMALY_BF527(< 2))

/* USB Calibration Value Is Not Initialized */

#define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2))

/* USB Calibration Value to use */

#define ANOMALY_05000346_value 0xE510

/* Preboot Routine Incorrectly Alters Reset Value of USB Register */

#define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000347 (_ANOMALY_BF527(< 2))

/* Security Features Are Not Functional */

#define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1)

#define ANOMALY_05000348 (_ANOMALY_BF527(< 1))

/* bfrom_SysControl() Firmware Function Performs Improper System Reset */

#define ANOMALY_05000353 (ANOMALY_BF526)

#define ANOMALY_05000353 (_ANOMALY_BF526(< 1))

/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */

#define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000355 (_ANOMALY_BF527(< 2))

/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */

#define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000357 (_ANOMALY_BF527(< 2))

/* Incorrect Revision Number in DSPID Register */

#define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1)

#define ANOMALY_05000364 (_ANOMALY_BF527(== 1))

/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */

#define ANOMALY_05000366 (1)

/* Incorrect Default CSEL Value in PLL_DIV */

#define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000368 (_ANOMALY_BF527(< 2))

/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */

#define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000371 (_ANOMALY_BF527(< 2))

/* Authentication Fails To Initiate */

#define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000376 (_ANOMALY_BF527(< 2))

/* Data Read From L3 Memory by USB DMA May be Corrupted */

#define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000380 (_ANOMALY_BF527(< 2))

/* 8-Bit NAND Flash Boot Mode Not Functional */

#define ANOMALY_05000382 (__SILICON_REVISION__ < 2)

/* Host Must Not Read Back During Host DMA Boot */

#define ANOMALY_05000384 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2))

/* Boot from OTP Memory Not Functional */

#define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000385 (_ANOMALY_BF527(< 2))

/* bfrom_SysControl() Firmware Routine Not Functional */

#define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000386 (_ANOMALY_BF527(< 2))

/* Programmable Preboot Settings Not Functional */

#define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000387 (_ANOMALY_BF527(< 2))

/* CRC32 Checksum Support Not Functional */

#define ANOMALY_05000388 (__SILICON_REVISION__ < 2)

#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2))

/* Reset Vector Must Not Be in SDRAM Memory Space */

#define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000389 (_ANOMALY_BF527(< 2))

/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */

#define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000392 (_ANOMALY_BF527(< 2))

/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */

#define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000393 (_ANOMALY_BF527(< 2))

/* Log Buffer Not Functional */

#define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000394 (_ANOMALY_BF527(< 2))

/* Hook Routine Not Functional */

#define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000395 (_ANOMALY_BF527(< 2))

/* Header Indirect Bit Not Functional */

#define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000396 (_ANOMALY_BF527(< 2))

/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */

#define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000397 (_ANOMALY_BF527(< 2))

/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */

#define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000398 (_ANOMALY_BF527(< 2))

/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */

#define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000399 (_ANOMALY_BF527(< 2))

/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */

#define ANOMALY_05000401 (__SILICON_REVISION__ < 2)

#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2))

/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */

#define ANOMALY_05000403 (__SILICON_REVISION__ < 2)

#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2))

/* Lockbox SESR Disallows Certain User Interrupts */

#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)

#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2))

/* Lockbox SESR Firmware Does Not Save/Restore Full Context */

#define ANOMALY_05000405 (1)

/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */

#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)

#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2))

/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */

#define ANOMALY_05000408 (1)

/* Lockbox firmware leaves MDMA0 channel enabled */

#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)

#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2))

/* Incorrect Default Internal Voltage Regulator Setting */

#define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))

/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */

#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)

#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2))

/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */

#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)

#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))

/* DEB2_URGENT Bit Not Functional */

#define ANOMALY_05000415 (__SILICON_REVISION__ < 2)

#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2))

/* Speculative Fetches Can Cause Undesired External FIFO Operations */

#define ANOMALY_05000416 (1)

/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */

#define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

/* tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */

#define ANOMALY_05000418 (__SILICON_REVISION__ < 2)

#define ANOMALY_05000417 (_ANOMALY_BF527(< 2))

/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */

#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2))

/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */

#define ANOMALY_05000420 (__SILICON_REVISION__ < 2)

#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2))

/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */

#define ANOMALY_05000421 (1)

/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */

#define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)

#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1))

/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */

#define ANOMALY_05000423 (__SILICON_REVISION__ < 2)

#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2))

/* Internal Voltage Regulator Not Trimmed */

#define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)

#define ANOMALY_05000424 (_ANOMALY_BF527(< 2))

/* Multichannel SPORT Channel Misalignment Under Specific Configuration */

#define ANOMALY_05000425 (__SILICON_REVISION__ < 2)

/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */

#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2))

/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */

#define ANOMALY_05000426 (1)

/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */

#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)

#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2))

/* Software System Reset Corrupts PLL_LOCKCNT Register */

#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)

#define ANOMALY_05000430 (_ANOMALY_BF527(> 1))

/* Incorrect Use of Stack in Lockbox Firmware During Authentication */

#define ANOMALY_05000431 (1)

/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */

#define ANOMALY_05000432 (ANOMALY_BF526)

#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))

/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */

#define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527)

#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))

/* Preboot Cannot be Used to Alter the PLL_DIV Register */

#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0))

/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */

#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0))

/* OTP Write Accesses Not Supported */

#define ANOMALY_05000442 (_ANOMALY_BF527(< 1))

/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */

#define ANOMALY_05000443 (1)

/* The WURESET Bit in the SYSCR Register is not Functional */

#define ANOMALY_05000445 (1)

/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */

#define ANOMALY_05000451 (1)

/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */

#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))

/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */

#define ANOMALY_05000456 (1)

/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */

#define ANOMALY_05000457 (1)

/* False Hardware Error when RETI points to invalid memory */

#define ANOMALY_05000461 (1)



/* Anomalies that don't exist on this proc */

#define ANOMALY_05000099 (0)

#define ANOMALY_05000120 (0)

#define ANOMALY_05000125 (0)

#define ANOMALY_05000149 (0)

#define ANOMALY_05000158 (0)

#define ANOMALY_05000171 (0)

#define ANOMALY_05000179 (0)

#define ANOMALY_05000183 (0)

#define ANOMALY_05000198 (0)

#define ANOMALY_05000215 (0)

#define ANOMALY_05000220 (0)

#define ANOMALY_05000227 (0)

#define ANOMALY_05000230 (0)

#define ANOMALY_05000231 (0)

#define ANOMALY_05000233 (0)

#define ANOMALY_05000242 (0)

#define ANOMALY_05000244 (0)

#define ANOMALY_05000248 (0)

#define ANOMALY_05000250 (0)

#define ANOMALY_05000261 (0)

#define ANOMALY_05000263 (0)

#define ANOMALY_05000266 (0)

#define ANOMALY_05000273 (0)

#define ANOMALY_05000274 (0)

#define ANOMALY_05000278 (0)

#define ANOMALY_05000285 (0)

#define ANOMALY_05000287 (0)

#define ANOMALY_05000301 (0)

#define ANOMALY_05000305 (0)

#define ANOMALY_05000307 (0)

#define ANOMALY_05000311 (0)

#define ANOMALY_05000312 (0)

#define ANOMALY_05000323 (0)

#define ANOMALY_05000362 (1)

#define ANOMALY_05000363 (0)

#define ANOMALY_05000400 (0)

#define ANOMALY_05000412 (0)

#define ANOMALY_05000447 (0)

#define ANOMALY_05000448 (0)

#define ANOMALY_05000450 (0)



#endif

arch/blackfin/mach-bf533/include/mach/anomaly.h

+74 −14

File changed.

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arch/blackfin/mach-bf537/include/mach/anomaly.h

+52 −32

File changed.

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arch/blackfin/mach-bf538/include/mach/anomaly.h

+47 −13
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ 
 * Licensed under the GPL-2 or later.

 */



/* This file shoule be up to date with:

/* This file should be up to date with:

 *  - Revision G, 09/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List

 *  - Revision L, 09/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List

 */
@@ -14,17 +14,29 @@ 
#ifndef _MACH_ANOMALY_H_

#define _MACH_ANOMALY_H_



/* We do not support old silicon - sorry */

#if __SILICON_REVISION__ < 4

# error will not work on BF538 silicon version 0.0, 0.1, 0.2, or 0.3

# error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3

#endif



/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */

#if defined(__ADSPBF538__)

# define ANOMALY_BF538 1

#else

# define ANOMALY_BF538 0

#endif

#if defined(__ADSPBF539__)

# define ANOMALY_BF539 1

#else

# define ANOMALY_BF539 0

#endif



/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */

#define ANOMALY_05000074 (1)

/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */

#define ANOMALY_05000119 (1)

/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */

#define ANOMALY_05000122 (1)

/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */

/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */

#define ANOMALY_05000166 (1)

/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */

#define ANOMALY_05000179 (1)
@@ -40,13 +52,13 @@ 
#define ANOMALY_05000229 (1)

/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */

#define ANOMALY_05000233 (1)

/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */

/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */

#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)

/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */

/* False Hardware Error from an Access in the Shadow of a Conditional Branch */

#define ANOMALY_05000245 (1)

/* Maximum External Clock Speed for Timers */

#define ANOMALY_05000253 (1)

/* DCPLB_FAULT_ADDR MMR register may be corrupted */

/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */

#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)

/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */

#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
@@ -58,11 +70,11 @@ 
#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)

/* Disabling Peripherals with DMA Running May Cause DMA System Instability */

#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)

/* False Hardware Error Exception when ISR Context Is Not Restored */

/* False Hardware Error Exception When ISR Context Is Not Restored */

#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)

/* Memory DMA Corruption with 32-Bit Data and Traffic Control */

#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)

/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */

/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */

#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)

/* SPORTs May Receive Bad Data If FIFOs Fill Up */

#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
@@ -80,14 +92,14 @@ 
#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)

/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */

#define ANOMALY_05000310 (1)

/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */

/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */

#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)

/* PPI Is Level-Sensitive on First Transfer */

/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */

#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)

/* Killed System MMR Write Completes Erroneously on Next System MMR Access */

/* Killed System MMR Write Completes Erroneously On Next System MMR Access */

#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)

/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */

#define ANOMALY_05000318 (__SILICON_REVISION__ < 4)

#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4)

/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */

#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)

/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
@@ -114,23 +126,45 @@ 
#define ANOMALY_05000436 (__SILICON_REVISION__ > 3)

/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */

#define ANOMALY_05000443 (1)

/* False Hardware Error when RETI points to invalid memory */

#define ANOMALY_05000461 (1)



/* Anomalies that don't exist on this proc */

#define ANOMALY_05000099 (0)

#define ANOMALY_05000120 (0)

#define ANOMALY_05000149 (0)

#define ANOMALY_05000158 (0)

#define ANOMALY_05000171 (0)

#define ANOMALY_05000198 (0)

#define ANOMALY_05000215 (0)

#define ANOMALY_05000220 (0)

#define ANOMALY_05000227 (0)

#define ANOMALY_05000230 (0)

#define ANOMALY_05000231 (0)

#define ANOMALY_05000242 (0)

#define ANOMALY_05000248 (0)

#define ANOMALY_05000250 (0)

#define ANOMALY_05000254 (0)

#define ANOMALY_05000263 (0)

#define ANOMALY_05000274 (0)

#define ANOMALY_05000287 (0)

#define ANOMALY_05000305 (0)

#define ANOMALY_05000311 (0)

#define ANOMALY_05000323 (0)

#define ANOMALY_05000353 (1)

#define ANOMALY_05000362 (1)

#define ANOMALY_05000363 (0)

#define ANOMALY_05000380 (0)

#define ANOMALY_05000386 (1)

#define ANOMALY_05000389 (0)

#define ANOMALY_05000400 (0)

#define ANOMALY_05000412 (0)

#define ANOMALY_05000430 (0)

#define ANOMALY_05000432 (0)

#define ANOMALY_05000435 (0)

#define ANOMALY_05000447 (0)

#define ANOMALY_05000448 (0)

#define ANOMALY_05000456 (0)

#define ANOMALY_05000450 (0)



#endif