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Commit a3ce3645 authored by Roger He's avatar Roger He Committed by Alex Deucher
Browse files

drm/amd/amdgpu: fix BANK_SELECT on Vega10 (v2) 



BANK_SELECT should always be FRAGMENT_SIZE + 3 due to 8-entry (2^3)
per cache line in L2 TLB for Vega10.

v2: agd: fix warning

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarRoger He <Hongbo.He@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1cacc86a

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+2 −3
Original line number Diff line number Diff line
@@ -124,7 +124,7 @@ static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 


static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)

{

	uint32_t tmp, field;

	uint32_t tmp;



	/* Setup L2 cache */

	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
@@ -143,9 +143,8 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

	WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);



	field = adev->vm_manager.fragment_size;

	tmp = mmVM_L2_CNTL3_DEFAULT;

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);

	WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+2 −3
Original line number Diff line number Diff line
@@ -138,7 +138,7 @@ static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 


static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)

{

	uint32_t tmp, field;

	uint32_t tmp;



	/* Setup L2 cache */

	tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
@@ -157,9 +157,8 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);



	field = adev->vm_manager.fragment_size;

	tmp = mmVM_L2_CNTL3_DEFAULT;

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);

	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);