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Commit a3ac3d4a authored by Yoshihiro Shimoda's avatar Yoshihiro Shimoda Committed by Kishon Vijay Abraham I
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phy: phy-rcar-gen2: Fix USBHS_UGSTS_LOCK value 



According to the technical update (No. TN-RCS-B011A/E), the UGSTS LOCK
bit location is bit 8, not bits 1 and 0. It also says that the register
address offset of UGSTS is 0x88, not 0x90.
So, this patch fixes the USBHS_UGSTS_LOCK value and some comments.

Signed-off-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parent 4581f798

drivers/phy/phy-rcar-gen2.c

+2 −2
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ 
#define USBHS_LPSTS			0x02

#define USBHS_UGCTRL			0x80

#define USBHS_UGCTRL2			0x84

#define USBHS_UGSTS			0x88	/* The manuals have 0x90 */

#define USBHS_UGSTS			0x88	/* From technical update */



/* Low Power Status register (LPSTS) */

#define USBHS_LPSTS_SUSPM		0x4000
@@ -41,7 +41,7 @@ 
#define USBHS_UGCTRL2_USB0SEL_HS_USB	0x00000030



/* USB General status register (UGSTS) */

#define USBHS_UGSTS_LOCK		0x00000300 /* The manuals have 0x3 */

#define USBHS_UGSTS_LOCK		0x00000100 /* From technical update */



#define PHYS_PER_CHANNEL	2