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Commit a2f72d39 authored by Gaurav Kohli's avatar Gaurav Kohli Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Move cache dump tables to memory dump allocations 

Currently cpu cache and tlb dump tables are getting allocated from
cpuss dump driver. Unify all the dump table allocations and move
cpu cache dump table entries to memory dump driver.

Change-Id: I4ff7c61191d174e4b17f8c0cda435c2779082ca4
parent b027e553

qcom/lito.dtsi

+160 −226
Original line number Diff line number Diff line
@@ -77,17 +77,12 @@ 


			L1_I_0: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x10800>;

			};



			L1_D_0: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_0: l2-tlb {

				qcom,dump-size = <0x5a00>;

			};

		};



		CPU1: cpu@100 {
@@ -110,17 +105,12 @@ 


			L1_I_100: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x10800>;

			};



			L1_D_100: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_100: l2-tlb {

				qcom,dump-size = <0x5a00>;

			};

		};



		CPU2: cpu@200 {
@@ -143,17 +133,12 @@ 


			L1_I_200: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x10800>;

			};



			L1_D_200: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_200: l2-tlb {

				qcom,dump-size = <0x5a00>;

			};

		};



		CPU3: cpu@300 {
@@ -176,16 +161,10 @@ 


			L1_I_300: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x10800>;

			};



			L1_D_300: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_300: l2-tlb {

				qcom,dump-size = <0x5a00>;

			};



		};
@@ -210,16 +189,10 @@ 


			L1_I_400: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x10800>;

			};



			L1_D_400: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_400: l2-tlb {

				qcom,dump-size = <0x5a00>;

			};

		};
@@ -243,16 +216,10 @@ 


			L1_I_500: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x10800>;

			};



			L1_D_500: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x9000>;

			};



			L2_TLB_500: l2-tlb {

				qcom,dump-size = <0x5a00>;

			};

		};
@@ -273,30 +240,16 @@ 
				cache-size = <0x40000>;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

				qcom,dump-size = <0x48000>;

			};



			L1_I_600: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x21000>;

			};



			L1_D_600: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x12000>;

			};



			L1_ITLB_600: l1-itlb {

				qcom,dump-size = <0x300>;

			};



			L1_DTLB_600: l1-dtlb {

				qcom,dump-size = <0x480>;

			};



			L2_TLB_600: l2-tlb {

				qcom,dump-size = <0x7800>;

			};

		};



		CPU7: cpu@700 {
@@ -316,29 +269,14 @@ 
				cache-size = <0x40000>;

				cache-level = <2>;

				next-level-cache = <&L3_0>;

				qcom,dump-size = <0x48000>;

			};



			L1_I_700: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x21000>;

			};



			L1_D_700: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x12000>;

			};



			L1_ITLB_700: l1-itlb {

				qcom,dump-size = <0x300>;

			};



			L1_DTLB_700: l1-dtlb {

				qcom,dump-size = <0x480>;

			};



			L2_TLB_700: l2-tlb {

				qcom,dump-size = <0x7800>;

			};

		};
@@ -1628,170 +1566,6 @@ 
		status = "ok";

	};



	cpuss_dump {

		compatible = "qcom,cpuss-dump";



		qcom,l1_i_cache0 {

			qcom,dump-node = <&L1_I_0>;

			qcom,dump-id = <0x60>;

		};



		qcom,l1_i_cache100 {

			qcom,dump-node = <&L1_I_100>;

			qcom,dump-id = <0x61>;

		};



		qcom,l1_i_cache200 {

			qcom,dump-node = <&L1_I_200>;

			qcom,dump-id = <0x62>;

		};



		qcom,l1_i_cache300 {

			qcom,dump-node = <&L1_I_300>;

			qcom,dump-id = <0x63>;

		};



		qcom,l1_i_cache400 {

			qcom,dump-node = <&L1_I_400>;

			qcom,dump-id = <0x64>;

		};



		qcom,l1_i_cache500 {

			qcom,dump-node = <&L1_I_500>;

			qcom,dump-id = <0x65>;

		};



		qcom,l1_i_cache600 {

			qcom,dump-node = <&L1_I_600>;

			qcom,dump-id = <0x66>;

		};



		qcom,l1_i_cache700 {

			qcom,dump-node = <&L1_I_700>;

			qcom,dump-id = <0x67>;

		};



		qcom,l1_d_cache0 {

			qcom,dump-node = <&L1_D_0>;

			qcom,dump-id = <0x80>;

		};



		qcom,l1_d_cache100 {

			qcom,dump-node = <&L1_D_100>;

			qcom,dump-id = <0x81>;

		};



		qcom,l1_d_cache200 {

			qcom,dump-node = <&L1_D_200>;

			qcom,dump-id = <0x82>;

		};



		qcom,l1_d_cache300 {

			qcom,dump-node = <&L1_D_300>;

			qcom,dump-id = <0x83>;

		};



		qcom,l1_d_cache400 {

			qcom,dump-node = <&L1_D_400>;

			qcom,dump-id = <0x84>;

		};



		qcom,l1_d_cache500 {

			qcom,dump-node = <&L1_D_500>;

			qcom,dump-id = <0x85>;

		};



		qcom,l1_d_cache600 {

			qcom,dump-node = <&L1_D_600>;

			qcom,dump-id = <0x86>;

		};



		qcom,l1_d_cache700 {

			qcom,dump-node = <&L1_D_700>;

			qcom,dump-id = <0x87>;

		};



		qcom,l1_i_tlb_dump600 {

			qcom,dump-node = <&L1_ITLB_600>;

			qcom,dump-id = <0x26>;

		};



		qcom,l1_i_tlb_dump700 {

			qcom,dump-node = <&L1_ITLB_700>;

			qcom,dump-id = <0x27>;

		};



		qcom,l1_d_tlb_dump600 {

			qcom,dump-node = <&L1_DTLB_600>;

			qcom,dump-id = <0x46>;

		};



		qcom,l1_d_tlb_dump700 {

			qcom,dump-node = <&L1_DTLB_700>;

			qcom,dump-id = <0x47>;

		};



		qcom,l2_cache_dump600 {

			qcom,dump-node = <&L2_600>;

			qcom,dump-id = <0xc6>;

		};



		qcom,l2_cache_dump700 {

			qcom,dump-node = <&L2_700>;

			qcom,dump-id = <0xc7>;

		};



		qcom,l2_tlb_dump0 {

			qcom,dump-node = <&L2_TLB_0>;

			qcom,dump-id = <0x120>;

		};



		qcom,l2_tlb_dump100 {

			qcom,dump-node = <&L2_TLB_100>;

			qcom,dump-id = <0x121>;

		};



		qcom,l2_tlb_dump200 {

			qcom,dump-node = <&L2_TLB_200>;

			qcom,dump-id = <0x122>;

		};



		qcom,l2_tlb_dump300 {

			qcom,dump-node = <&L2_TLB_300>;

			qcom,dump-id = <0x123>;

		};



		qcom,l2_tlb_dump400 {

			qcom,dump-node = <&L2_TLB_400>;

			qcom,dump-id = <0x124>;

		};



		qcom,l2_tlb_dump500 {

			qcom,dump-node = <&L2_TLB_500>;

			qcom,dump-id = <0x125>;

		};



		qcom,l2_tlb_dump600 {

			qcom,dump-node = <&L2_TLB_600>;

			qcom,dump-id = <0x126>;

		};



		qcom,l2_tlb_dump700 {

			qcom,dump-node = <&L2_TLB_700>;

			qcom,dump-id = <0x127>;

		};



		qcom,llcc1_d_cache {

			qcom,dump-node = <&LLCC_1>;

			qcom,dump-id = <0x140>;

		};



		qcom,llcc2_d_cache {

			qcom,dump-node = <&LLCC_2>;

			qcom,dump-id = <0x141>;

		};

	};



	qcom,sps {

		compatible = "qcom,msm-sps-4k";

		qcom,pipe-attr-ee;
@@ -2450,6 +2224,166 @@ 
		compatible = "qcom,mem-dump";

		memory-region = <&dump_mem>;



		l1_icache0 {

			qcom,dump-size = <0x10800>;

			qcom,dump-id = <0x60>;

		};



		l1_icache100 {

			qcom,dump-size = <0x10800>;

			qcom,dump-id = <0x61>;

		};



		l1_icache200 {

			qcom,dump-size = <0x10800>;

			qcom,dump-id = <0x62>;

		};



		l1_icache300 {

			qcom,dump-size = <0x10800>;

			qcom,dump-id = <0x63>;

		};



		l1_icache400 {

			qcom,dump-size = <0x10800>;

			qcom,dump-id = <0x64>;

		};



		l1_icache500 {

			qcom,dump-size = <0x10800>;

			qcom,dump-id = <0x65>;

		};



		l1_icache600 {

			qcom,dump-size = <0x21000>;

			qcom,dump-id = <0x66>;

		};



		l1_icache700 {

			qcom,dump-size = <0x21000>;

			qcom,dump-id = <0x67>;

		};



		l1_dcache0 {

			qcom,dump-size = <0x9000>;

			qcom,dump-id = <0x80>;

		};



		l1_dcache100 {

			qcom,dump-size = <0x9000>;

			qcom,dump-id = <0x81>;

		};



		l1_dcache200 {

			qcom,dump-size = <0x9000>;

			qcom,dump-id = <0x82>;

		};



		l1_dcache300 {

			qcom,dump-size = <0x9000>;

			qcom,dump-id = <0x83>;

		};



		l1_dcache400 {

			qcom,dump-size = <0x9000>;

			qcom,dump-id = <0x84>;

		};



		l1_dcache500 {

			qcom,dump-size = <0x9000>;

			qcom,dump-id = <0x85>;

		};



		l1_dcache600 {

			qcom,dump-size = <0x12000>;

			qcom,dump-id = <0x86>;

		};



		l1_dcache700 {

			qcom,dump-size = <0x12000>;

			qcom,dump-id = <0x87>;

		};



		l1_itlb600 {

			qcom,dump-size = <0x300>;

			qcom,dump-id = <0x26>;

		};



		l1_itlb700 {

			qcom,dump-size = <0x300>;

			qcom,dump-id = <0x27>;

		};



		l1_dtlb600 {

			qcom,dump-size = <0x480>;

			qcom,dump-id = <0x46>;

		};



		l1_dtlb700 {

			qcom,dump-size = <0x480>;

			qcom,dump-id = <0x47>;

		};



		l2_cache600 {

			qcom,dump-size = <0x48000>;

			qcom,dump-id = <0xc6>;

		};



		l2_cache700 {

			qcom,dump-size = <0x48000>;

			qcom,dump-id = <0xc7>;

		};



		l2_tlb0 {

			qcom,dump-size = <0x5a00>;

			qcom,dump-id = <0x120>;

		};



		l2_tlb100 {

			qcom,dump-size = <0x5a00>;

			qcom,dump-id = <0x121>;

		};



		l2_tlb200 {

			qcom,dump-size = <0x5a00>;

			qcom,dump-id = <0x122>;

		};



		l2_tlb300 {

			qcom,dump-size = <0x5a00>;

			qcom,dump-id = <0x123>;

		};



		l2_tlb400 {

			qcom,dump-size = <0x5a00>;

			qcom,dump-id = <0x124>;

		};



		l2_tlb500 {

			qcom,dump-size = <0x5a00>;

			qcom,dump-id = <0x125>;

		};



		l2_tlb600 {

			qcom,dump-size = <0x7800>;

			qcom,dump-id = <0x126>;

		};



		l2_tlb700 {

			qcom,dump-size = <0x7800>;

			qcom,dump-id = <0x127>;

		};



		llcc1_d_cache {

			qcom,dump-size = <0x1141c0>;

			qcom,dump-id = <0x140>;

		};



		llcc2_d_cache {

			qcom,dump-size = <0x1141c0>;

			qcom,dump-id = <0x141>;

		};



		rpmh {

			qcom,dump-size = <0x2000000>;

			qcom,dump-id = <0xec>;