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Commit a2c09c12 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-at91', 'clk-imx7ulp', 'clk-axigen', 'clk-si5351' and 'clk-pxa' into clk-next 

* clk-at91:
  clk: at91: pmc: Support backup for programmable clocks
  clk: at91: pmc: Save SCSR during suspend
  clk: at91: pmc: Wait for clocks when resuming

* clk-imx7ulp:
  clk: Don't touch hardware when reparenting during registration

* clk-axigen:
  clk: axi-clkgen: Round closest in round_rate() and recalc_rate()
  clk: axi-clkgen: Correctly handle nocount bit in recalc_rate()

* clk-si5351:
  clk: si5351: _si5351_clkout_reset_pll() can be static
  clk: si5351: Do not enable parent clocks on probe
  clk: si5351: Rename internal plls to avoid name collisions
  clk: si5351: Apply PLL soft reset before enabling the outputs
  clk: si5351: Add DT property to enable PLL reset
  clk: si5351: implement remove handler

* clk-pxa:
  clk: pxa: unbreak lookup of CLK_POUT
parents 21170e3b 13967bea f8f8f1d0 448c3c05 0136f852 869de5cf

Documentation/devicetree/bindings/clock/silabs,si5351.txt

+1 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ Optional child node properties: 
- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth

  divider.

- silabs,pll-master: boolean, multisynth can change pll frequency.

- silabs,pll-reset: boolean, clock output can reset its pll.

- silabs,disable-state : clock output disable state, shall be

  0 = clock output is driven LOW when disabled

  1 = clock output is driven HIGH when disabled

drivers/clk/at91/clk-programmable.c

+2 −0
Original line number Diff line number Diff line
@@ -204,6 +204,8 @@ at91_clk_register_programmable(struct regmap *regmap, 
	if (ret) {

		kfree(prog);

		hw = ERR_PTR(ret);

	} else {

		pmc_register_pck(id);

	}



	return hw;

drivers/clk/at91/pmc.c

+53 −10
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#include "pmc.h"



#define PMC_MAX_IDS 128

#define PMC_MAX_PCKS 8



int of_at91_get_clk_range(struct device_node *np, const char *propname,

			  struct clk_range *range)
@@ -50,6 +51,7 @@ EXPORT_SYMBOL_GPL(of_at91_get_clk_range); 
static struct regmap *pmcreg;



static u8 registered_ids[PMC_MAX_IDS];

static u8 registered_pcks[PMC_MAX_PCKS];



static struct

{
@@ -66,8 +68,13 @@ static struct 
	u32 pcr[PMC_MAX_IDS];

	u32 audio_pll0;

	u32 audio_pll1;

	u32 pckr[PMC_MAX_PCKS];

} pmc_cache;



/*

 * As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored

 * without alteration in the table, and 0 is for unused clocks.

 */

void pmc_register_id(u8 id)

{

	int i;
@@ -82,11 +89,30 @@ void pmc_register_id(u8 id) 
	}

}



/*

 * As Programmable Clock 0 is valid on AT91 chips, there is an offset

 * of 1 between the stored value and the real clock ID.

 */

void pmc_register_pck(u8 pck)

{

	int i;



	for (i = 0; i < PMC_MAX_PCKS; i++) {

		if (registered_pcks[i] == 0) {

			registered_pcks[i] = pck + 1;

			break;

		}

		if (registered_pcks[i] == (pck + 1))

			break;

	}

}



static int pmc_suspend(void)

{

	int i;

	u8 num;



	regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.scsr);

	regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr);

	regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0);

	regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr);

	regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor);
@@ -103,14 +129,29 @@ static int pmc_suspend(void) 
		regmap_read(pmcreg, AT91_PMC_PCR,

			    &pmc_cache.pcr[registered_ids[i]]);

	}

	for (i = 0; registered_pcks[i]; i++) {

		num = registered_pcks[i] - 1;

		regmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]);

	}



	return 0;

}



static bool pmc_ready(unsigned int mask)

{

	unsigned int status;



	regmap_read(pmcreg, AT91_PMC_SR, &status);



	return ((status & mask) == mask) ? 1 : 0;

}



static void pmc_resume(void)

{

	int i, ret = 0;

	int i;

	u8 num;

	u32 tmp;

	u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA;



	regmap_read(pmcreg, AT91_PMC_MCKR, &tmp);

	if (pmc_cache.mckr != tmp)
@@ -119,7 +160,7 @@ static void pmc_resume(void) 
	if (pmc_cache.pllar != tmp)

		pr_warn("PLLAR was not configured properly by the firmware\n");



	regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.scsr);

	regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr);

	regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0);

	regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr);

	regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor);
@@ -133,14 +174,16 @@ static void pmc_resume(void) 
			     pmc_cache.pcr[registered_ids[i]] |

			     AT91_PMC_PCR_CMD);

	}



	if (pmc_cache.uckr & AT91_PMC_UPLLEN) {

		ret = regmap_read_poll_timeout(pmcreg, AT91_PMC_SR, tmp,

					       !(tmp & AT91_PMC_LOCKU),

					       10, 5000);

		if (ret)

			pr_crit("USB PLL didn't lock when resuming\n");

	for (i = 0; registered_pcks[i]; i++) {

		num = registered_pcks[i] - 1;

		regmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]);

	}



	if (pmc_cache.uckr & AT91_PMC_UPLLEN)

		mask |= AT91_PMC_LOCKU;



	while (!pmc_ready(mask))

		cpu_relax();

}



static struct syscore_ops pmc_syscore_ops = {

drivers/clk/at91/pmc.h

+2 −0
Original line number Diff line number Diff line
@@ -31,8 +31,10 @@ int of_at91_get_clk_range(struct device_node *np, const char *propname, 


#ifdef CONFIG_PM

void pmc_register_id(u8 id);

void pmc_register_pck(u8 pck);

#else

static inline void pmc_register_id(u8 id) {}

static inline void pmc_register_pck(u8 pck) {}

#endif



#endif /* __PMC_H_ */

drivers/clk/clk-axi-clkgen.c

+31 −8
Original line number Diff line number Diff line
@@ -40,6 +40,10 @@ 
#define MMCM_REG_FILTER1	0x4e

#define MMCM_REG_FILTER2	0x4f



#define MMCM_CLKOUT_NOCOUNT	BIT(6)



#define MMCM_CLK_DIV_NOCOUNT	BIT(12)



struct axi_clkgen {

	void __iomem *base;

	struct clk_hw clk_hw;
@@ -298,13 +302,17 @@ static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate, 
	unsigned long *parent_rate)

{

	unsigned int d, m, dout;

	unsigned long long tmp;



	axi_clkgen_calc_params(*parent_rate, rate, &d, &m, &dout);



	if (d == 0 || dout == 0 || m == 0)

		return -EINVAL;



	return *parent_rate / d * m / dout;

	tmp = (unsigned long long)*parent_rate * m;

	tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);



	return min_t(unsigned long long, tmp, LONG_MAX);

}



static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
@@ -315,18 +323,33 @@ static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw, 
	unsigned int reg;

	unsigned long long tmp;



	axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_2, &reg);

	if (reg & MMCM_CLKOUT_NOCOUNT) {

		dout = 1;

	} else {

		axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_1, &reg);

		dout = (reg & 0x3f) + ((reg >> 6) & 0x3f);

	}



	axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &reg);

	if (reg & MMCM_CLK_DIV_NOCOUNT)

		d = 1;

	else

		d = (reg & 0x3f) + ((reg >> 6) & 0x3f);



	axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB2, &reg);

	if (reg & MMCM_CLKOUT_NOCOUNT) {

		m = 1;

	} else {

		axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB1, &reg);

		m = (reg & 0x3f) + ((reg >> 6) & 0x3f);

	}



	if (d == 0 || dout == 0)

		return 0;



	tmp = (unsigned long long)(parent_rate / d) * m;

	do_div(tmp, dout);

	tmp = (unsigned long long)parent_rate * m;

	tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);



	return min_t(unsigned long long, tmp, ULONG_MAX);

}