Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a29cb8c4 authored by Daniel Kurtz's avatar Daniel Kurtz Committed by Heiko Stuebner
Browse files

ARM: dts: rockchip: Add rk3288 vop and display-subsystem 



Add devicetree nodes for rk3288 VOP (Video Output Processors), and the
top level display-subsystem root node.

Later patches add endpoints (eDP, HDMI, LVDS, etc) that attach to the
VOPs' output ports.

Signed-off-by: default avatarDaniel Kurtz <djkurtz@chromium.org>
Signed-off-by: default avatarMark yao <mark.yao@rock-chips.com>
Reviewed-by: default avatarStephane Marchesin <marcheu@chromium.org>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 5963e106

arch/arm/boot/dts/rk3288.dtsi

+39 −0
Original line number Original line Diff line number Diff line
@@ -149,6 +149,11 @@ 
		clock-frequency = <24000000>;

		clock-frequency = <24000000>;

	};

	};





	display-subsystem {

		compatible = "rockchip,display-subsystem";

		ports = <&vopl_out>, <&vopb_out>;

	};



	sdmmc: dwmmc@ff0c0000 {

	sdmmc: dwmmc@ff0c0000 {

		compatible = "rockchip,rk3288-dw-mshc";

		compatible = "rockchip,rk3288-dw-mshc";

		clock-freq-min-max = <400000 150000000>;

		clock-freq-min-max = <400000 150000000>;
@@ -566,6 +571,23 @@ 
		status = "disabled";

		status = "disabled";

	};

	};





	vopb: vop@ff930000 {

		compatible = "rockchip,rk3288-vop";

		reg = <0xff930000 0x19c>;

		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;

		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";

		resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;

		reset-names = "axi", "ahb", "dclk";

		iommus = <&vopb_mmu>;

		status = "disabled";



		vopb_out: port {

			#address-cells = <1>;

			#size-cells = <0>;

		};

	};



	vopb_mmu: iommu@ff930300 {

	vopb_mmu: iommu@ff930300 {

		compatible = "rockchip,iommu";

		compatible = "rockchip,iommu";

		reg = <0xff930300 0x100>;

		reg = <0xff930300 0x100>;
@@ -575,6 +597,23 @@ 
		status = "disabled";

		status = "disabled";

	};

	};





	vopl: vop@ff940000 {

		compatible = "rockchip,rk3288-vop";

		reg = <0xff940000 0x19c>;

		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;

		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";

		resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;

		reset-names = "axi", "ahb", "dclk";

		iommus = <&vopl_mmu>;

		status = "disabled";



		vopl_out: port {

			#address-cells = <1>;

			#size-cells = <0>;

		};

	};



	vopl_mmu: iommu@ff940300 {

	vopl_mmu: iommu@ff940300 {

		compatible = "rockchip,iommu";

		compatible = "rockchip,iommu";

		reg = <0xff940300 0x100>;

		reg = <0xff940300 0x100>;