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Commit a26cf1c9 authored by Michael Ellerman's avatar Michael Ellerman
Browse files

Merge branch 'topic/ppc-kvm' into next 

This brings in two series from Paul, one of which touches KVM code and
may need to be merged into the kvm-ppc tree to resolve conflicts.
parents 78e5dfea 681c617b

arch/powerpc/include/asm/asm-prototypes.h

+3 −0
Original line number Diff line number Diff line
@@ -138,4 +138,7 @@ extern int __ucmpdi2(u64, u64); 
void _mcount(void);

unsigned long prepare_ftrace_return(unsigned long parent, unsigned long ip);



void pnv_power9_force_smt4_catch(void);

void pnv_power9_force_smt4_release(void);



#endif /* _ASM_POWERPC_ASM_PROTOTYPES_H */

arch/powerpc/include/asm/cputable.h

+117 −113
Original line number Diff line number Diff line
@@ -131,41 +131,48 @@ static inline void cpu_feature_keys_init(void) { } 


/* CPU kernel features */



/* Retain the 32b definitions all use bottom half of word */

/* Definitions for features that we have on both 32-bit and 64-bit chips */

#define CPU_FTR_COHERENT_ICACHE		ASM_CONST(0x00000001)

#define CPU_FTR_L2CR			ASM_CONST(0x00000002)

#define CPU_FTR_SPEC7450		ASM_CONST(0x00000004)

#define CPU_FTR_ALTIVEC			ASM_CONST(0x00000008)

#define CPU_FTR_TAU			ASM_CONST(0x00000010)

#define CPU_FTR_CAN_DOZE		ASM_CONST(0x00000020)

#define CPU_FTR_USE_TB			ASM_CONST(0x00000040)

#define CPU_FTR_L2CSR			ASM_CONST(0x00000080)

#define CPU_FTR_601			ASM_CONST(0x00000100)

#define CPU_FTR_DBELL			ASM_CONST(0x00000200)

#define CPU_FTR_CAN_NAP			ASM_CONST(0x00000400)

#define CPU_FTR_L3CR			ASM_CONST(0x00000800)

#define CPU_FTR_L3_DISABLE_NAP		ASM_CONST(0x00001000)

#define CPU_FTR_NAP_DISABLE_L2_PR	ASM_CONST(0x00002000)

#define CPU_FTR_DUAL_PLL_750FX		ASM_CONST(0x00004000)

#define CPU_FTR_NO_DPM			ASM_CONST(0x00008000)

#define CPU_FTR_476_DD2			ASM_CONST(0x00010000)

#define CPU_FTR_NEED_COHERENT		ASM_CONST(0x00020000)

#define CPU_FTR_NO_BTIC			ASM_CONST(0x00040000)

#define CPU_FTR_DEBUG_LVL_EXC		ASM_CONST(0x00080000)

#define CPU_FTR_NODSISRALIGN		ASM_CONST(0x00100000)

#define CPU_FTR_PPC_LE			ASM_CONST(0x00200000)

#define CPU_FTR_REAL_LE			ASM_CONST(0x00400000)

#define CPU_FTR_FPU_UNAVAILABLE		ASM_CONST(0x00800000)

#define CPU_FTR_UNIFIED_ID_CACHE	ASM_CONST(0x01000000)

#define CPU_FTR_SPE			ASM_CONST(0x02000000)

#define CPU_FTR_NEED_PAIRED_STWCX	ASM_CONST(0x04000000)

#define CPU_FTR_LWSYNC			ASM_CONST(0x08000000)

#define CPU_FTR_NOEXECUTE		ASM_CONST(0x10000000)

#define CPU_FTR_INDEXED_DCR		ASM_CONST(0x20000000)

#define CPU_FTR_EMB_HV			ASM_CONST(0x40000000)

#define CPU_FTR_ALTIVEC			ASM_CONST(0x00000002)

#define CPU_FTR_DBELL			ASM_CONST(0x00000004)

#define CPU_FTR_CAN_NAP			ASM_CONST(0x00000008)

#define CPU_FTR_DEBUG_LVL_EXC		ASM_CONST(0x00000010)

#define CPU_FTR_NODSISRALIGN		ASM_CONST(0x00000020)

#define CPU_FTR_FPU_UNAVAILABLE		ASM_CONST(0x00000040)

#define CPU_FTR_LWSYNC			ASM_CONST(0x00000080)

#define CPU_FTR_NOEXECUTE		ASM_CONST(0x00000100)

#define CPU_FTR_EMB_HV			ASM_CONST(0x00000200)



/* Definitions for features that only exist on 32-bit chips */

#ifdef CONFIG_PPC32

#define CPU_FTR_601			ASM_CONST(0x00001000)

#define CPU_FTR_L2CR			ASM_CONST(0x00002000)

#define CPU_FTR_SPEC7450		ASM_CONST(0x00004000)

#define CPU_FTR_TAU			ASM_CONST(0x00008000)

#define CPU_FTR_CAN_DOZE		ASM_CONST(0x00010000)

#define CPU_FTR_USE_RTC			ASM_CONST(0x00020000)

#define CPU_FTR_L3CR			ASM_CONST(0x00040000)

#define CPU_FTR_L3_DISABLE_NAP		ASM_CONST(0x00080000)

#define CPU_FTR_NAP_DISABLE_L2_PR	ASM_CONST(0x00100000)

#define CPU_FTR_DUAL_PLL_750FX		ASM_CONST(0x00200000)

#define CPU_FTR_NO_DPM			ASM_CONST(0x00400000)

#define CPU_FTR_476_DD2			ASM_CONST(0x00800000)

#define CPU_FTR_NEED_COHERENT		ASM_CONST(0x01000000)

#define CPU_FTR_NO_BTIC			ASM_CONST(0x02000000)

#define CPU_FTR_PPC_LE			ASM_CONST(0x04000000)

#define CPU_FTR_UNIFIED_ID_CACHE	ASM_CONST(0x08000000)

#define CPU_FTR_SPE			ASM_CONST(0x10000000)

#define CPU_FTR_NEED_PAIRED_STWCX	ASM_CONST(0x20000000)

#define CPU_FTR_INDEXED_DCR		ASM_CONST(0x40000000)



#else	/* CONFIG_PPC32 */

/* Define these to 0 for the sake of tests in common code */

#define CPU_FTR_601			(0)

#define CPU_FTR_PPC_LE			(0)

#endif



/*

 * Add the 64-bit processor unique features in the top half of the word;

 * Definitions for the 64-bit processor unique features;

 * on 32-bit, make the names available but defined to be 0.

 */

#ifdef __powerpc64__
@@ -174,37 +181,40 @@ static inline void cpu_feature_keys_init(void) { } 
#define LONG_ASM_CONST(x)		0

#endif



#define CPU_FTR_HVMODE			LONG_ASM_CONST(0x0000000100000000)

#define CPU_FTR_ARCH_201		LONG_ASM_CONST(0x0000000200000000)

#define CPU_FTR_ARCH_206		LONG_ASM_CONST(0x0000000400000000)

#define CPU_FTR_ARCH_207S		LONG_ASM_CONST(0x0000000800000000)

#define CPU_FTR_ARCH_300		LONG_ASM_CONST(0x0000001000000000)

#define CPU_FTR_MMCRA			LONG_ASM_CONST(0x0000002000000000)

#define CPU_FTR_CTRL			LONG_ASM_CONST(0x0000004000000000)

#define CPU_FTR_SMT			LONG_ASM_CONST(0x0000008000000000)

#define CPU_FTR_PAUSE_ZERO		LONG_ASM_CONST(0x0000010000000000)

#define CPU_FTR_PURR			LONG_ASM_CONST(0x0000020000000000)

#define CPU_FTR_CELL_TB_BUG		LONG_ASM_CONST(0x0000040000000000)

#define CPU_FTR_SPURR			LONG_ASM_CONST(0x0000080000000000)

#define CPU_FTR_DSCR			LONG_ASM_CONST(0x0000100000000000)

#define CPU_FTR_VSX			LONG_ASM_CONST(0x0000200000000000)

#define CPU_FTR_SAO			LONG_ASM_CONST(0x0000400000000000)

#define CPU_FTR_CP_USE_DCBTZ		LONG_ASM_CONST(0x0000800000000000)

#define CPU_FTR_UNALIGNED_LD_STD	LONG_ASM_CONST(0x0001000000000000)

#define CPU_FTR_ASYM_SMT		LONG_ASM_CONST(0x0002000000000000)

#define CPU_FTR_STCX_CHECKS_ADDRESS	LONG_ASM_CONST(0x0004000000000000)

#define CPU_FTR_POPCNTB			LONG_ASM_CONST(0x0008000000000000)

#define CPU_FTR_POPCNTD			LONG_ASM_CONST(0x0010000000000000)

#define CPU_FTR_PKEY			LONG_ASM_CONST(0x0020000000000000)

#define CPU_FTR_VMX_COPY		LONG_ASM_CONST(0x0040000000000000)

#define CPU_FTR_TM			LONG_ASM_CONST(0x0080000000000000)

#define CPU_FTR_CFAR			LONG_ASM_CONST(0x0100000000000000)

#define	CPU_FTR_HAS_PPR			LONG_ASM_CONST(0x0200000000000000)

#define CPU_FTR_DAWR			LONG_ASM_CONST(0x0400000000000000)

#define CPU_FTR_DABRX			LONG_ASM_CONST(0x0800000000000000)

#define CPU_FTR_PMAO_BUG		LONG_ASM_CONST(0x1000000000000000)

#define CPU_FTR_POWER9_DD1		LONG_ASM_CONST(0x4000000000000000)

#define CPU_FTR_POWER9_DD2_1		LONG_ASM_CONST(0x8000000000000000)

#define CPU_FTR_REAL_LE			LONG_ASM_CONST(0x0000000000001000)

#define CPU_FTR_HVMODE			LONG_ASM_CONST(0x0000000000002000)

#define CPU_FTR_ARCH_201		LONG_ASM_CONST(0x0000000000004000)

#define CPU_FTR_ARCH_206		LONG_ASM_CONST(0x0000000000008000)

#define CPU_FTR_ARCH_207S		LONG_ASM_CONST(0x0000000000010000)

#define CPU_FTR_ARCH_300		LONG_ASM_CONST(0x0000000000020000)

#define CPU_FTR_MMCRA			LONG_ASM_CONST(0x0000000000040000)

#define CPU_FTR_CTRL			LONG_ASM_CONST(0x0000000000080000)

#define CPU_FTR_SMT			LONG_ASM_CONST(0x0000000000100000)

#define CPU_FTR_PAUSE_ZERO		LONG_ASM_CONST(0x0000000000200000)

#define CPU_FTR_PURR			LONG_ASM_CONST(0x0000000000400000)

#define CPU_FTR_CELL_TB_BUG		LONG_ASM_CONST(0x0000000000800000)

#define CPU_FTR_SPURR			LONG_ASM_CONST(0x0000000001000000)

#define CPU_FTR_DSCR			LONG_ASM_CONST(0x0000000002000000)

#define CPU_FTR_VSX			LONG_ASM_CONST(0x0000000004000000)

#define CPU_FTR_SAO			LONG_ASM_CONST(0x0000000008000000)

#define CPU_FTR_CP_USE_DCBTZ		LONG_ASM_CONST(0x0000000010000000)

#define CPU_FTR_UNALIGNED_LD_STD	LONG_ASM_CONST(0x0000000020000000)

#define CPU_FTR_ASYM_SMT		LONG_ASM_CONST(0x0000000040000000)

#define CPU_FTR_STCX_CHECKS_ADDRESS	LONG_ASM_CONST(0x0000000080000000)

#define CPU_FTR_POPCNTB			LONG_ASM_CONST(0x0000000100000000)

#define CPU_FTR_POPCNTD			LONG_ASM_CONST(0x0000000200000000)

#define CPU_FTR_PKEY			LONG_ASM_CONST(0x0000000400000000)

#define CPU_FTR_VMX_COPY		LONG_ASM_CONST(0x0000000800000000)

#define CPU_FTR_TM			LONG_ASM_CONST(0x0000001000000000)

#define CPU_FTR_CFAR			LONG_ASM_CONST(0x0000002000000000)

#define	CPU_FTR_HAS_PPR			LONG_ASM_CONST(0x0000004000000000)

#define CPU_FTR_DAWR			LONG_ASM_CONST(0x0000008000000000)

#define CPU_FTR_DABRX			LONG_ASM_CONST(0x0000010000000000)

#define CPU_FTR_PMAO_BUG		LONG_ASM_CONST(0x0000020000000000)

#define CPU_FTR_POWER9_DD1		LONG_ASM_CONST(0x0000040000000000)

#define CPU_FTR_POWER9_DD2_1		LONG_ASM_CONST(0x0000080000000000)

#define CPU_FTR_P9_TM_HV_ASSIST		LONG_ASM_CONST(0x0000100000000000)

#define CPU_FTR_P9_TM_XER_SO_BUG	LONG_ASM_CONST(0x0000200000000000)



#ifndef __ASSEMBLY__
@@ -285,21 +295,19 @@ static inline void cpu_feature_keys_init(void) { } 
#endif



#define CPU_FTRS_PPC601	(CPU_FTR_COMMON | CPU_FTR_601 | \

	CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)

#define CPU_FTRS_603	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \

	CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_USE_RTC)

#define CPU_FTRS_603	(CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)

#define CPU_FTRS_604	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | CPU_FTR_PPC_LE)

#define CPU_FTRS_604	(CPU_FTR_COMMON | CPU_FTR_PPC_LE)

#define CPU_FTRS_740_NOTAU	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)

#define CPU_FTRS_740	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \

	    CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_PPC_LE)

#define CPU_FTRS_750	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \

	    CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_PPC_LE)

#define CPU_FTRS_750CL	(CPU_FTRS_750)
@@ -308,125 +316,118 @@ static inline void cpu_feature_keys_init(void) { } 
#define CPU_FTRS_750FX	(CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)

#define CPU_FTRS_750GX	(CPU_FTRS_750FX)

#define CPU_FTRS_7400_NOTAU	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \

	    CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)

#define CPU_FTRS_7400	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \

	    CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)

#define CPU_FTRS_7450_20	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7450_21	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7450_23	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \

	    CPU_FTR_NEED_PAIRED_STWCX | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)

#define CPU_FTRS_7455_1	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \

	    CPU_FTR_NEED_PAIRED_STWCX | \

	    CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \

	    CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)

#define CPU_FTRS_7455_20	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \

	    CPU_FTR_NEED_PAIRED_STWCX | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)

#define CPU_FTRS_7455	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7447_10	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \

	    CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7447	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7447A	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_7448	(CPU_FTR_COMMON | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \

	    CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)

#define CPU_FTRS_82XX	(CPU_FTR_COMMON | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)

#define CPU_FTRS_82XX	(CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE)

#define CPU_FTRS_G2_LE	(CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \

	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)

	    CPU_FTR_MAYBE_CAN_NAP)

#define CPU_FTRS_E300	(CPU_FTR_MAYBE_CAN_DOZE | \

	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_COMMON)

#define CPU_FTRS_E300C2	(CPU_FTR_MAYBE_CAN_DOZE | \

	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)

#define CPU_FTRS_CLASSIC32	(CPU_FTR_COMMON | CPU_FTR_USE_TB)

#define CPU_FTRS_8XX	(CPU_FTR_USE_TB | CPU_FTR_NOEXECUTE)

#define CPU_FTRS_40X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)

#define CPU_FTRS_44X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)

#define CPU_FTRS_440x6	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \

#define CPU_FTRS_CLASSIC32	(CPU_FTR_COMMON)

#define CPU_FTRS_8XX	(CPU_FTR_NOEXECUTE)

#define CPU_FTRS_40X	(CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)

#define CPU_FTRS_44X	(CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)

#define CPU_FTRS_440x6	(CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \

	    CPU_FTR_INDEXED_DCR)

#define CPU_FTRS_47X	(CPU_FTRS_440x6)

#define CPU_FTRS_E200	(CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \

#define CPU_FTRS_E200	(CPU_FTR_SPE_COMP | \

	    CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \

	    CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \

	    CPU_FTR_DEBUG_LVL_EXC)

#define CPU_FTRS_E500	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \

#define CPU_FTRS_E500	(CPU_FTR_MAYBE_CAN_DOZE | \

	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \

	    CPU_FTR_NOEXECUTE)

#define CPU_FTRS_E500_2	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \

#define CPU_FTRS_E500_2	(CPU_FTR_MAYBE_CAN_DOZE | \

	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)

#define CPU_FTRS_E500MC	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \

	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \

#define CPU_FTRS_E500MC	(CPU_FTR_NODSISRALIGN | \

	    CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \

	    CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)

/*

 * e5500/e6500 erratum A-006958 is a timebase bug that can use the

 * same workaround as CPU_FTR_CELL_TB_BUG.

 */

#define CPU_FTRS_E5500	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \

	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \

#define CPU_FTRS_E5500	(CPU_FTR_NODSISRALIGN | \

	    CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \

	    CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \

	    CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)

#define CPU_FTRS_E6500	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \

	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \

#define CPU_FTRS_E6500	(CPU_FTR_NODSISRALIGN | \

	    CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \

	    CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \

	    CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)

#define CPU_FTRS_GENERIC_32	(CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)



/* 64-bit CPUs */

#define CPU_FTRS_POWER4	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_POWER4	(CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \

	    CPU_FTR_STCX_CHECKS_ADDRESS)

#define CPU_FTRS_PPC970	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_PPC970	(CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \

	    CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \

	    CPU_FTR_HVMODE | CPU_FTR_DABRX)

#define CPU_FTRS_POWER5	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_POWER5	(CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)

#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | \
@@ -434,7 +435,7 @@ static inline void cpu_feature_keys_init(void) { } 
	    CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \

	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \

	    CPU_FTR_DABRX)

#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | \
@@ -443,7 +444,7 @@ static inline void cpu_feature_keys_init(void) { } 
	    CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \

	    CPU_FTR_CFAR | CPU_FTR_HVMODE | \

	    CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX | CPU_FTR_PKEY)

#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | \
@@ -455,7 +456,7 @@ static inline void cpu_feature_keys_init(void) { } 
	    CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_PKEY)

#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)

#define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)

#define CPU_FTRS_POWER9 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\

	    CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_COHERENT_ICACHE | \
@@ -470,15 +471,17 @@ static inline void cpu_feature_keys_init(void) { } 
			     (~CPU_FTR_SAO))

#define CPU_FTRS_POWER9_DD2_0 CPU_FTRS_POWER9

#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1)

#define CPU_FTRS_CELL	(CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_P9_TM_HV_ASSIST | \

			       CPU_FTR_P9_TM_XER_SO_BUG)

#define CPU_FTRS_CELL	(CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \

	    CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \

	    CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)

#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \

#define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)

#define CPU_FTRS_COMPATIBLE	(CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)

#define CPU_FTRS_COMPATIBLE	(CPU_FTR_PPCAS_ARCH_V2)



#ifdef __powerpc64__

#ifdef CONFIG_PPC_BOOK3E
@@ -489,7 +492,8 @@ static inline void cpu_feature_keys_init(void) { } 
	     CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \

	     CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \

	     CPU_FTRS_PA6T | CPU_FTR_VSX | CPU_FTRS_POWER9 | \

	     CPU_FTRS_POWER9_DD1 | CPU_FTRS_POWER9_DD2_1)

	     CPU_FTRS_POWER9_DD1 | CPU_FTRS_POWER9_DD2_1 | \

	     CPU_FTRS_POWER9_DD2_2)

#endif

#else

enum {

arch/powerpc/include/asm/kvm_asm.h

+2 −0
Original line number Diff line number Diff line
@@ -108,6 +108,8 @@ 


/* book3s_hv */



#define BOOK3S_INTERRUPT_HV_SOFTPATCH	0x1500



/*

 * Special trap used to indicate to host that this is a

 * passthrough interrupt that could not be handled

arch/powerpc/include/asm/kvm_book3s.h

+4 −0
Original line number Diff line number Diff line
@@ -241,6 +241,10 @@ extern void kvmppc_update_lpcr(struct kvm *kvm, unsigned long lpcr, 
			unsigned long mask);

extern void kvmppc_set_fscr(struct kvm_vcpu *vcpu, u64 fscr);



extern int kvmhv_p9_tm_emulation_early(struct kvm_vcpu *vcpu);

extern int kvmhv_p9_tm_emulation(struct kvm_vcpu *vcpu);

extern void kvmhv_emulate_tm_rollback(struct kvm_vcpu *vcpu);



extern void kvmppc_entry_trampoline(void);

extern void kvmppc_hv_entry_trampoline(void);

extern u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst);

arch/powerpc/include/asm/kvm_book3s_64.h

+43 −0
Original line number Diff line number Diff line
@@ -472,6 +472,49 @@ static inline void set_dirty_bits_atomic(unsigned long *map, unsigned long i, 
			set_bit_le(i, map);

}



static inline u64 sanitize_msr(u64 msr)

{

	msr &= ~MSR_HV;

	msr |= MSR_ME;

	return msr;

}



#ifdef CONFIG_PPC_TRANSACTIONAL_MEM

static inline void copy_from_checkpoint(struct kvm_vcpu *vcpu)

{

	vcpu->arch.cr  = vcpu->arch.cr_tm;

	vcpu->arch.xer = vcpu->arch.xer_tm;

	vcpu->arch.lr  = vcpu->arch.lr_tm;

	vcpu->arch.ctr = vcpu->arch.ctr_tm;

	vcpu->arch.amr = vcpu->arch.amr_tm;

	vcpu->arch.ppr = vcpu->arch.ppr_tm;

	vcpu->arch.dscr = vcpu->arch.dscr_tm;

	vcpu->arch.tar = vcpu->arch.tar_tm;

	memcpy(vcpu->arch.gpr, vcpu->arch.gpr_tm,

	       sizeof(vcpu->arch.gpr));

	vcpu->arch.fp  = vcpu->arch.fp_tm;

	vcpu->arch.vr  = vcpu->arch.vr_tm;

	vcpu->arch.vrsave = vcpu->arch.vrsave_tm;

}



static inline void copy_to_checkpoint(struct kvm_vcpu *vcpu)

{

	vcpu->arch.cr_tm  = vcpu->arch.cr;

	vcpu->arch.xer_tm = vcpu->arch.xer;

	vcpu->arch.lr_tm  = vcpu->arch.lr;

	vcpu->arch.ctr_tm = vcpu->arch.ctr;

	vcpu->arch.amr_tm = vcpu->arch.amr;

	vcpu->arch.ppr_tm = vcpu->arch.ppr;

	vcpu->arch.dscr_tm = vcpu->arch.dscr;

	vcpu->arch.tar_tm = vcpu->arch.tar;

	memcpy(vcpu->arch.gpr_tm, vcpu->arch.gpr,

	       sizeof(vcpu->arch.gpr));

	vcpu->arch.fp_tm  = vcpu->arch.fp;

	vcpu->arch.vr_tm  = vcpu->arch.vr;

	vcpu->arch.vrsave_tm = vcpu->arch.vrsave;

}

#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */



#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */



#endif /* __ASM_KVM_BOOK3S_64_H__ */