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Commit a26a3f53 authored by Pardha Saradhi K's avatar Pardha Saradhi K Committed by Mark Brown
Browse files

ASoC: Intel: Skylake: Add support for programming D0i3C 



To set the controller in D0i3 mode, the driver needs to set D0i3C
register after DSP is quiesced. Since the D0iX entry/exit is done by IPC,
add this as callback so that it can be invoked from IPC module.

Signed-off-by: default avatarPardha Saradhi K <pardha.saradhi.kesapragada@intel.com>
Signed-off-by: default avatarJayachandran B <jayachandran.b@intel.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 41b7523f

sound/soc/intel/skylake/skl-pcm.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -1211,6 +1211,7 @@ static int skl_platform_soc_probe(struct snd_soc_platform *platform) 
			return ret;

			return ret;

		}

		}

		skl_populate_modules(skl);

		skl_populate_modules(skl);

		skl->skl_sst->update_d0i3c = skl_update_d0i3c;

	}

	}

	pm_runtime_mark_last_busy(platform->dev);

	pm_runtime_mark_last_busy(platform->dev);

	pm_runtime_put_autosuspend(platform->dev);

	pm_runtime_put_autosuspend(platform->dev);

sound/soc/intel/skylake/skl-sst-ipc.h

+3 −0
Original line number Original line Diff line number Diff line
@@ -83,6 +83,9 @@ struct skl_sst { 




	/* tplg manifest */

	/* tplg manifest */

	struct skl_dfw_manifest manifest;

	struct skl_dfw_manifest manifest;



	/* Callback to update D0i3C register */

	void (*update_d0i3c)(struct device *dev, bool enable);

};

};





struct skl_ipc_init_instance_msg {

struct skl_ipc_init_instance_msg {

sound/soc/intel/skylake/skl.c

+47 −0
Original line number Original line Diff line number Diff line
@@ -26,6 +26,7 @@ 
#include <linux/pm_runtime.h>

#include <linux/pm_runtime.h>

#include <linux/platform_device.h>

#include <linux/platform_device.h>

#include <linux/firmware.h>

#include <linux/firmware.h>

#include <linux/delay.h>

#include <sound/pcm.h>

#include <sound/pcm.h>

#include "../common/sst-acpi.h"

#include "../common/sst-acpi.h"

#include <sound/hda_register.h>

#include <sound/hda_register.h>
@@ -109,6 +110,52 @@ static int skl_init_chip(struct hdac_bus *bus, bool full_reset) 
	return ret;

	return ret;

}

}





void skl_update_d0i3c(struct device *dev, bool enable)

{

	struct pci_dev *pci = to_pci_dev(dev);

	struct hdac_ext_bus *ebus = pci_get_drvdata(pci);

	struct hdac_bus *bus = ebus_to_hbus(ebus);

	u8 reg;

	int timeout = 50;



	reg = snd_hdac_chip_readb(bus, VS_D0I3C);

	/* Do not write to D0I3C until command in progress bit is cleared */

	while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {

		udelay(10);

		reg = snd_hdac_chip_readb(bus, VS_D0I3C);

	}



	/* Highly unlikely. But if it happens, flag error explicitly */

	if (!timeout) {

		dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n");

		return;

	}



	if (enable)

		reg = reg | AZX_REG_VS_D0I3C_I3;

	else

		reg = reg & (~AZX_REG_VS_D0I3C_I3);



	snd_hdac_chip_writeb(bus, VS_D0I3C, reg);



	timeout = 50;

	/* Wait for cmd in progress to be cleared before exiting the function */

	reg = snd_hdac_chip_readb(bus, VS_D0I3C);

	while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {

		udelay(10);

		reg = snd_hdac_chip_readb(bus, VS_D0I3C);

	}



	/* Highly unlikely. But if it happens, flag error explicitly */

	if (!timeout) {

		dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n");

		return;

	}



	dev_dbg(bus->dev, "D0I3C register = 0x%x\n",

			snd_hdac_chip_readb(bus, VS_D0I3C));

}



/* called from IRQ */

/* called from IRQ */

static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)

static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)

{

{

sound/soc/intel/skylake/skl.h

+5 −0
Original line number Original line Diff line number Diff line
@@ -52,6 +52,9 @@ 
#define AZX_PGCTL_LSRMD_MASK		(1 << 4)

#define AZX_PGCTL_LSRMD_MASK		(1 << 4)

#define AZX_PCIREG_CGCTL		0x48

#define AZX_PCIREG_CGCTL		0x48

#define AZX_CGCTL_MISCBDCGE_MASK	(1 << 6)

#define AZX_CGCTL_MISCBDCGE_MASK	(1 << 6)

/* D0I3C Register fields */

#define AZX_REG_VS_D0I3C_CIP      0x1 /* Command in progress */

#define AZX_REG_VS_D0I3C_I3       0x4 /* D0i3 enable */





struct skl_dsp_resource {

struct skl_dsp_resource {

	u32 max_mcps;

	u32 max_mcps;
@@ -125,4 +128,6 @@ int skl_suspend_dsp(struct skl *skl); 
int skl_resume_dsp(struct skl *skl);

int skl_resume_dsp(struct skl *skl);

void skl_cleanup_resources(struct skl *skl);

void skl_cleanup_resources(struct skl *skl);

const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id);

const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id);

void skl_update_d0i3c(struct device *dev, bool enable);



#endif /* __SOUND_SOC_SKL_H */
 
#endif /* __SOUND_SOC_SKL_H */