Loading drivers/bus/mhi/controllers/mhi_arch_qcom.c +22 −64 Original line number Diff line number Diff line Loading @@ -31,8 +31,6 @@ struct arch_info { void *boot_ipc_log; void *tsync_ipc_log; struct mhi_device *boot_dev; struct mhi_link_info current_link_info; struct work_struct bw_scale_work; bool drv_connected; struct notifier_block pm_notifier; struct completion pm_completion; Loading Loading @@ -367,49 +365,13 @@ static int mhi_arch_pcie_scale_bw(struct mhi_controller *mhi_cntrl, return 0; } static void mhi_arch_pcie_bw_scale_work(struct work_struct *work) static int mhi_arch_bw_scale(struct mhi_controller *mhi_cntrl, struct mhi_link_info *link_info) { struct arch_info *arch_info = container_of(work, struct arch_info, bw_scale_work); struct mhi_dev *mhi_dev = arch_info->mhi_dev; struct mhi_dev *mhi_dev = mhi_controller_get_devdata(mhi_cntrl); struct pci_dev *pci_dev = mhi_dev->pci_dev; struct device *dev = &pci_dev->dev; struct mhi_controller *mhi_cntrl = dev_get_drvdata(dev); struct mhi_link_info mhi_link_info; struct mhi_link_info *cur_info = &arch_info->current_link_info; int ret; mutex_lock(&mhi_cntrl->pm_mutex); if (!mhi_dev->powered_on || MHI_IS_SUSPENDED(mhi_dev->suspend_mode)) goto exit_work; /* copy the latest speed change */ write_lock_irq(&mhi_cntrl->pm_lock); mhi_link_info = mhi_cntrl->mhi_link_info; write_unlock_irq(&mhi_cntrl->pm_lock); /* link is already set to current settings */ if (cur_info->target_link_speed == mhi_link_info.target_link_speed && cur_info->target_link_width == mhi_link_info.target_link_width) goto exit_work; ret = mhi_arch_pcie_scale_bw(mhi_cntrl, pci_dev, &mhi_link_info); if (ret) goto exit_work; *cur_info = mhi_link_info; exit_work: mutex_unlock(&mhi_cntrl->pm_mutex); } static void mhi_arch_pcie_bw_scale_cb(struct mhi_controller *mhi_cntrl, struct mhi_dev *mhi_dev) { struct arch_info *arch_info = mhi_dev->arch_info; schedule_work(&arch_info->bw_scale_work); return mhi_arch_pcie_scale_bw(mhi_cntrl, pci_dev, link_info); } static int mhi_bl_probe(struct mhi_device *mhi_device, Loading Loading @@ -566,9 +528,7 @@ int mhi_arch_pcie_init(struct mhi_controller *mhi_cntrl) mhi_dev->pci_dev, NULL, 0); mhi_dev->pci_dev->no_d3hot = true; INIT_WORK(&arch_info->bw_scale_work, mhi_arch_pcie_bw_scale_work); mhi_dev->bw_scale = mhi_arch_pcie_bw_scale_cb; mhi_cntrl->bw_scale = mhi_arch_bw_scale; /* store the current bw info */ ret = pcie_capability_read_word(mhi_dev->pci_dev, Loading @@ -576,13 +536,12 @@ int mhi_arch_pcie_init(struct mhi_controller *mhi_cntrl) if (ret) return ret; cur_link_info = &arch_info->current_link_info; cur_link_info = &mhi_cntrl->mhi_link_info; cur_link_info->target_link_speed = linkstat & PCI_EXP_LNKSTA_CLS; cur_link_info->target_link_width = (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; mhi_cntrl->mhi_link_info = *cur_link_info; mhi_driver_register(&mhi_bl_driver); } Loading @@ -598,13 +557,12 @@ void mhi_arch_pcie_deinit(struct mhi_controller *mhi_cntrl) static int mhi_arch_drv_suspend(struct mhi_controller *mhi_cntrl) { struct mhi_dev *mhi_dev = mhi_controller_get_devdata(mhi_cntrl); struct arch_info *arch_info = mhi_dev->arch_info; struct pci_dev *pci_dev = mhi_dev->pci_dev; struct mhi_link_info link_info, *cur_link_info; bool bw_switched = false; int ret; cur_link_info = &arch_info->current_link_info; cur_link_info = &mhi_cntrl->mhi_link_info; /* if link is not in gen 1 we need to switch to gen 1 */ if (cur_link_info->target_link_speed != PCI_EXP_LNKSTA_CLS_2_5GB) { link_info.target_link_speed = PCI_EXP_LNKSTA_CLS_2_5GB; Loading @@ -630,9 +588,6 @@ static int mhi_arch_drv_suspend(struct mhi_controller *mhi_cntrl) return ret; } if (bw_switched) *cur_link_info = link_info; return ret; } Loading Loading @@ -689,7 +644,7 @@ static int __mhi_arch_link_resume(struct mhi_controller *mhi_cntrl) struct mhi_dev *mhi_dev = mhi_controller_get_devdata(mhi_cntrl); struct arch_info *arch_info = mhi_dev->arch_info; struct pci_dev *pci_dev = mhi_dev->pci_dev; struct mhi_link_info *cur_info = &arch_info->current_link_info; struct mhi_link_info *cur_info = &mhi_cntrl->mhi_link_info; int ret; MHI_LOG("Entered\n"); Loading Loading @@ -733,10 +688,8 @@ static int __mhi_arch_link_resume(struct mhi_controller *mhi_cntrl) int mhi_arch_link_resume(struct mhi_controller *mhi_cntrl) { struct mhi_dev *mhi_dev = mhi_controller_get_devdata(mhi_cntrl); struct arch_info *arch_info = mhi_dev->arch_info; struct pci_dev *pci_dev = mhi_dev->pci_dev; struct mhi_link_info *cur_info = &arch_info->current_link_info; struct mhi_link_info *updated_info = &mhi_cntrl->mhi_link_info; struct mhi_link_info *cur_info = &mhi_cntrl->mhi_link_info; int ret = 0; MHI_LOG("Entered\n"); Loading @@ -748,6 +701,19 @@ int mhi_arch_link_resume(struct mhi_controller *mhi_cntrl) case MHI_FAST_LINK_OFF: ret = msm_pcie_pm_control(MSM_PCIE_RESUME, mhi_cntrl->bus, pci_dev, NULL, 0); if (ret || cur_info->target_link_speed == PCI_EXP_LNKSTA_CLS_2_5GB) break; /* * BW request from device isn't for gen 1 link speed, we can * only print an error here. */ if (mhi_arch_pcie_scale_bw(mhi_cntrl, pci_dev, cur_info)) MHI_ERR( "Failed to honor bw request: speed:0x%x width:0x%x\n", cur_info->target_link_speed, cur_info->target_link_width); break; case MHI_ACTIVE_STATE: case MHI_FAST_LINK_ON: Loading @@ -759,14 +725,6 @@ int mhi_arch_link_resume(struct mhi_controller *mhi_cntrl) return ret; } /* BW request from device doesn't match current link speed */ if (cur_info->target_link_speed != updated_info->target_link_speed || cur_info->target_link_width != updated_info->target_link_width) { ret = mhi_arch_pcie_scale_bw(mhi_cntrl, pci_dev, updated_info); if (!ret) *cur_info = *updated_info; } msm_pcie_l1ss_timeout_enable(pci_dev); MHI_LOG("Exited\n"); Loading drivers/bus/mhi/controllers/mhi_qcom.c +0 −4 Original line number Diff line number Diff line Loading @@ -609,10 +609,6 @@ static void mhi_status_cb(struct mhi_controller *mhi_cntrl, pm_runtime_mark_last_busy(dev); pm_request_autosuspend(dev); break; case MHI_CB_BW_REQ: if (mhi_dev->bw_scale) mhi_dev->bw_scale(mhi_cntrl, mhi_dev); break; case MHI_CB_EE_MISSION_MODE: /* * we need to force a suspend so device can switch to Loading drivers/bus/mhi/controllers/mhi_qcom.h +0 −3 Original line number Diff line number Diff line Loading @@ -48,9 +48,6 @@ struct mhi_dev { dma_addr_t iova_stop; enum mhi_suspend_mode suspend_mode; /* if set, soc support dynamic bw scaling */ void (*bw_scale)(struct mhi_controller *mhi_cntrl, struct mhi_dev *mhi_dev); unsigned int lpm_disable_depth; /* lock to toggle low power modes */ spinlock_t lpm_lock; Loading drivers/platform/msm/ipa/ipa_v3/ipa_mpm.c +0 −1 Original line number Diff line number Diff line Loading @@ -2419,7 +2419,6 @@ static void ipa_mpm_mhi_status_cb(struct mhi_device *mhi_dev, case MHI_CB_PENDING_DATA: case MHI_CB_SYS_ERROR: case MHI_CB_FATAL_ERROR: case MHI_CB_BW_REQ: case MHI_CB_EE_MISSION_MODE: IPA_MPM_ERR("unexpected event %d\n", mhi_cb); break; Loading include/linux/mhi.h +0 −2 Original line number Diff line number Diff line Loading @@ -23,7 +23,6 @@ struct mhi_buf_info; * @MHI_CB_EE_MISSION_MODE: MHI device entered Mission Mode ee * @MHI_CB_SYS_ERROR: MHI device enter error state (may recover) * @MHI_CB_FATAL_ERROR: MHI device entered fatal error * @MHI_CB_BW_REQ: Received a bandwidth switch request from device */ enum MHI_CB { MHI_CB_IDLE, Loading @@ -34,7 +33,6 @@ enum MHI_CB { MHI_CB_EE_MISSION_MODE, MHI_CB_SYS_ERROR, MHI_CB_FATAL_ERROR, MHI_CB_BW_REQ, }; /** Loading Loading
drivers/bus/mhi/controllers/mhi_arch_qcom.c +22 −64 Original line number Diff line number Diff line Loading @@ -31,8 +31,6 @@ struct arch_info { void *boot_ipc_log; void *tsync_ipc_log; struct mhi_device *boot_dev; struct mhi_link_info current_link_info; struct work_struct bw_scale_work; bool drv_connected; struct notifier_block pm_notifier; struct completion pm_completion; Loading Loading @@ -367,49 +365,13 @@ static int mhi_arch_pcie_scale_bw(struct mhi_controller *mhi_cntrl, return 0; } static void mhi_arch_pcie_bw_scale_work(struct work_struct *work) static int mhi_arch_bw_scale(struct mhi_controller *mhi_cntrl, struct mhi_link_info *link_info) { struct arch_info *arch_info = container_of(work, struct arch_info, bw_scale_work); struct mhi_dev *mhi_dev = arch_info->mhi_dev; struct mhi_dev *mhi_dev = mhi_controller_get_devdata(mhi_cntrl); struct pci_dev *pci_dev = mhi_dev->pci_dev; struct device *dev = &pci_dev->dev; struct mhi_controller *mhi_cntrl = dev_get_drvdata(dev); struct mhi_link_info mhi_link_info; struct mhi_link_info *cur_info = &arch_info->current_link_info; int ret; mutex_lock(&mhi_cntrl->pm_mutex); if (!mhi_dev->powered_on || MHI_IS_SUSPENDED(mhi_dev->suspend_mode)) goto exit_work; /* copy the latest speed change */ write_lock_irq(&mhi_cntrl->pm_lock); mhi_link_info = mhi_cntrl->mhi_link_info; write_unlock_irq(&mhi_cntrl->pm_lock); /* link is already set to current settings */ if (cur_info->target_link_speed == mhi_link_info.target_link_speed && cur_info->target_link_width == mhi_link_info.target_link_width) goto exit_work; ret = mhi_arch_pcie_scale_bw(mhi_cntrl, pci_dev, &mhi_link_info); if (ret) goto exit_work; *cur_info = mhi_link_info; exit_work: mutex_unlock(&mhi_cntrl->pm_mutex); } static void mhi_arch_pcie_bw_scale_cb(struct mhi_controller *mhi_cntrl, struct mhi_dev *mhi_dev) { struct arch_info *arch_info = mhi_dev->arch_info; schedule_work(&arch_info->bw_scale_work); return mhi_arch_pcie_scale_bw(mhi_cntrl, pci_dev, link_info); } static int mhi_bl_probe(struct mhi_device *mhi_device, Loading Loading @@ -566,9 +528,7 @@ int mhi_arch_pcie_init(struct mhi_controller *mhi_cntrl) mhi_dev->pci_dev, NULL, 0); mhi_dev->pci_dev->no_d3hot = true; INIT_WORK(&arch_info->bw_scale_work, mhi_arch_pcie_bw_scale_work); mhi_dev->bw_scale = mhi_arch_pcie_bw_scale_cb; mhi_cntrl->bw_scale = mhi_arch_bw_scale; /* store the current bw info */ ret = pcie_capability_read_word(mhi_dev->pci_dev, Loading @@ -576,13 +536,12 @@ int mhi_arch_pcie_init(struct mhi_controller *mhi_cntrl) if (ret) return ret; cur_link_info = &arch_info->current_link_info; cur_link_info = &mhi_cntrl->mhi_link_info; cur_link_info->target_link_speed = linkstat & PCI_EXP_LNKSTA_CLS; cur_link_info->target_link_width = (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; mhi_cntrl->mhi_link_info = *cur_link_info; mhi_driver_register(&mhi_bl_driver); } Loading @@ -598,13 +557,12 @@ void mhi_arch_pcie_deinit(struct mhi_controller *mhi_cntrl) static int mhi_arch_drv_suspend(struct mhi_controller *mhi_cntrl) { struct mhi_dev *mhi_dev = mhi_controller_get_devdata(mhi_cntrl); struct arch_info *arch_info = mhi_dev->arch_info; struct pci_dev *pci_dev = mhi_dev->pci_dev; struct mhi_link_info link_info, *cur_link_info; bool bw_switched = false; int ret; cur_link_info = &arch_info->current_link_info; cur_link_info = &mhi_cntrl->mhi_link_info; /* if link is not in gen 1 we need to switch to gen 1 */ if (cur_link_info->target_link_speed != PCI_EXP_LNKSTA_CLS_2_5GB) { link_info.target_link_speed = PCI_EXP_LNKSTA_CLS_2_5GB; Loading @@ -630,9 +588,6 @@ static int mhi_arch_drv_suspend(struct mhi_controller *mhi_cntrl) return ret; } if (bw_switched) *cur_link_info = link_info; return ret; } Loading Loading @@ -689,7 +644,7 @@ static int __mhi_arch_link_resume(struct mhi_controller *mhi_cntrl) struct mhi_dev *mhi_dev = mhi_controller_get_devdata(mhi_cntrl); struct arch_info *arch_info = mhi_dev->arch_info; struct pci_dev *pci_dev = mhi_dev->pci_dev; struct mhi_link_info *cur_info = &arch_info->current_link_info; struct mhi_link_info *cur_info = &mhi_cntrl->mhi_link_info; int ret; MHI_LOG("Entered\n"); Loading Loading @@ -733,10 +688,8 @@ static int __mhi_arch_link_resume(struct mhi_controller *mhi_cntrl) int mhi_arch_link_resume(struct mhi_controller *mhi_cntrl) { struct mhi_dev *mhi_dev = mhi_controller_get_devdata(mhi_cntrl); struct arch_info *arch_info = mhi_dev->arch_info; struct pci_dev *pci_dev = mhi_dev->pci_dev; struct mhi_link_info *cur_info = &arch_info->current_link_info; struct mhi_link_info *updated_info = &mhi_cntrl->mhi_link_info; struct mhi_link_info *cur_info = &mhi_cntrl->mhi_link_info; int ret = 0; MHI_LOG("Entered\n"); Loading @@ -748,6 +701,19 @@ int mhi_arch_link_resume(struct mhi_controller *mhi_cntrl) case MHI_FAST_LINK_OFF: ret = msm_pcie_pm_control(MSM_PCIE_RESUME, mhi_cntrl->bus, pci_dev, NULL, 0); if (ret || cur_info->target_link_speed == PCI_EXP_LNKSTA_CLS_2_5GB) break; /* * BW request from device isn't for gen 1 link speed, we can * only print an error here. */ if (mhi_arch_pcie_scale_bw(mhi_cntrl, pci_dev, cur_info)) MHI_ERR( "Failed to honor bw request: speed:0x%x width:0x%x\n", cur_info->target_link_speed, cur_info->target_link_width); break; case MHI_ACTIVE_STATE: case MHI_FAST_LINK_ON: Loading @@ -759,14 +725,6 @@ int mhi_arch_link_resume(struct mhi_controller *mhi_cntrl) return ret; } /* BW request from device doesn't match current link speed */ if (cur_info->target_link_speed != updated_info->target_link_speed || cur_info->target_link_width != updated_info->target_link_width) { ret = mhi_arch_pcie_scale_bw(mhi_cntrl, pci_dev, updated_info); if (!ret) *cur_info = *updated_info; } msm_pcie_l1ss_timeout_enable(pci_dev); MHI_LOG("Exited\n"); Loading
drivers/bus/mhi/controllers/mhi_qcom.c +0 −4 Original line number Diff line number Diff line Loading @@ -609,10 +609,6 @@ static void mhi_status_cb(struct mhi_controller *mhi_cntrl, pm_runtime_mark_last_busy(dev); pm_request_autosuspend(dev); break; case MHI_CB_BW_REQ: if (mhi_dev->bw_scale) mhi_dev->bw_scale(mhi_cntrl, mhi_dev); break; case MHI_CB_EE_MISSION_MODE: /* * we need to force a suspend so device can switch to Loading
drivers/bus/mhi/controllers/mhi_qcom.h +0 −3 Original line number Diff line number Diff line Loading @@ -48,9 +48,6 @@ struct mhi_dev { dma_addr_t iova_stop; enum mhi_suspend_mode suspend_mode; /* if set, soc support dynamic bw scaling */ void (*bw_scale)(struct mhi_controller *mhi_cntrl, struct mhi_dev *mhi_dev); unsigned int lpm_disable_depth; /* lock to toggle low power modes */ spinlock_t lpm_lock; Loading
drivers/platform/msm/ipa/ipa_v3/ipa_mpm.c +0 −1 Original line number Diff line number Diff line Loading @@ -2419,7 +2419,6 @@ static void ipa_mpm_mhi_status_cb(struct mhi_device *mhi_dev, case MHI_CB_PENDING_DATA: case MHI_CB_SYS_ERROR: case MHI_CB_FATAL_ERROR: case MHI_CB_BW_REQ: case MHI_CB_EE_MISSION_MODE: IPA_MPM_ERR("unexpected event %d\n", mhi_cb); break; Loading
include/linux/mhi.h +0 −2 Original line number Diff line number Diff line Loading @@ -23,7 +23,6 @@ struct mhi_buf_info; * @MHI_CB_EE_MISSION_MODE: MHI device entered Mission Mode ee * @MHI_CB_SYS_ERROR: MHI device enter error state (may recover) * @MHI_CB_FATAL_ERROR: MHI device entered fatal error * @MHI_CB_BW_REQ: Received a bandwidth switch request from device */ enum MHI_CB { MHI_CB_IDLE, Loading @@ -34,7 +33,6 @@ enum MHI_CB { MHI_CB_EE_MISSION_MODE, MHI_CB_SYS_ERROR, MHI_CB_FATAL_ERROR, MHI_CB_BW_REQ, }; /** Loading