Merge tag 'tags/renesas-dt-du-for-v3.19' into drm/next/adv7511-base (a218df07) · Commits · e / devices / android_kernel_oneplus_sm7250

arch/arm/boot/dts/r8a7779-marzen.dts

+83 −0

Original line number	Diff line number	Diff line
		@@ -68,6 +68,78 @@
		gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
		};
		};

		vga-encoder {
		compatible = "adi,adv7123";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		vga_enc_in: endpoint {
		remote-endpoint = <&du_out_rgb0>;
		};
		};
		port@1 {
		reg = <1>;
		vga_enc_out: endpoint {
		remote-endpoint = <&vga_in>;
		};
		};
		};
		};

		vga {
		compatible = "vga-connector";

		port {
		vga_in: endpoint {
		remote-endpoint = <&vga_enc_out>;
		};
		};
		};

		lvds-encoder {
		compatible = "thine,thc63lvdm83d";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		lvds_enc_in: endpoint {
		remote-endpoint = <&du_out_rgb1>;
		};
		};
		port@1 {
		reg = <1>;
		lvds_connector: endpoint {
		};
		};
		};
		};
		};

		&du {
		pinctrl-0 = <&du_pins>;
		pinctrl-names = "default";
		status = "okay";

		ports {
		port@0 {
		endpoint {
		remote-endpoint = <&vga_enc_in>;
		};
		};
		port@1 {
		endpoint {
		remote-endpoint = <&lvds_enc_in>;
		};
		};
		};
		};

		&irqpin0 {
		@@ -83,6 +155,17 @@
		};

		&pfc {
		du_pins: du {
		du0 {
		renesas,groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0";
		renesas,function = "du0";
		};
		du1 {
		renesas,groups = "du1_rgb666", "du1_sync_1", "du1_clk_out";
		renesas,function = "du1";
		};
		};

		lan0_pins: lan0 {
		intc {
		renesas,groups = "intc_irq1_b";

arch/arm/boot/dts/r8a7779.dtsi

+24 −0

Original line number	Diff line number	Diff line
		@@ -379,6 +379,30 @@
		status = "disabled";
		};

		du: display@fff80000 {
		compatible = "renesas,du-r8a7779";
		reg = <0 0xfff80000 0 0x40000>;
		interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7779_CLK_DU>;
		status = "disabled";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		du_out_rgb0: endpoint {
		};
		};
		port@1 {
		reg = <1>;
		du_out_rgb1: endpoint {
		};
		};
		};
		};

		clocks {
		#address-cells = <1>;
		#size-cells = <1>;

arch/arm/boot/dts/r8a7790-lager.dts

+50 −3

Original line number	Diff line number	Diff line
		@@ -144,16 +144,63 @@
		states = <3300000 1
		1800000 0>;
		};

		vga-encoder {
		compatible = "adi,adv7123";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		adv7123_in: endpoint {
		remote-endpoint = <&du_out_rgb>;
		};
		};
		port@1 {
		reg = <1>;
		adv7123_out: endpoint {
		remote-endpoint = <&vga_in>;
		};
		};
		};
		};

		&extal_clk {
		clock-frequency = <20000000>;
		vga {
		compatible = "vga-connector";

		port {
		vga_in: endpoint {
		remote-endpoint = <&adv7123_out>;
		};
		};
		};
		};

		&pfc {
		&du {
		pinctrl-0 = <&du_pins>;
		pinctrl-names = "default";
		status = "okay";

		ports {
		port@0 {
		endpoint {
		remote-endpoint = <&adv7123_in>;
		};
		};
		port@2 {
		lvds_connector: endpoint {
		};
		};
		};
		};

		&extal_clk {
		clock-frequency = <20000000>;
		};

		&pfc {
		du_pins: du {
		renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
		renesas,function = "du";

arch/arm/boot/dts/r8a7790.dtsi

+90 −0

Original line number	Diff line number	Diff line
		@@ -600,6 +600,96 @@
		status = "disabled";
		};

		vsp1@fe920000 {
		compatible = "renesas,vsp1";
		reg = <0 0xfe920000 0 0x8000>;
		interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;

		renesas,has-sru;
		renesas,#rpf = <5>;
		renesas,#uds = <1>;
		renesas,#wpf = <4>;
		};

		vsp1@fe928000 {
		compatible = "renesas,vsp1";
		reg = <0 0xfe928000 0 0x8000>;
		interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;

		renesas,has-lut;
		renesas,has-sru;
		renesas,#rpf = <5>;
		renesas,#uds = <3>;
		renesas,#wpf = <4>;
		};

		vsp1@fe930000 {
		compatible = "renesas,vsp1";
		reg = <0 0xfe930000 0 0x8000>;
		interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;

		renesas,has-lif;
		renesas,has-lut;
		renesas,#rpf = <4>;
		renesas,#uds = <1>;
		renesas,#wpf = <4>;
		};

		vsp1@fe938000 {
		compatible = "renesas,vsp1";
		reg = <0 0xfe938000 0 0x8000>;
		interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;

		renesas,has-lif;
		renesas,has-lut;
		renesas,#rpf = <4>;
		renesas,#uds = <1>;
		renesas,#wpf = <4>;
		};

		du: display@feb00000 {
		compatible = "renesas,du-r8a7790";
		reg = <0 0xfeb00000 0 0x70000>,
		<0 0xfeb90000 0 0x1c>,
		<0 0xfeb94000 0 0x1c>;
		reg-names = "du", "lvds.0", "lvds.1";
		interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
		<0 268 IRQ_TYPE_LEVEL_HIGH>,
		<0 269 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7790_CLK_DU0>,
		<&mstp7_clks R8A7790_CLK_DU1>,
		<&mstp7_clks R8A7790_CLK_DU2>,
		<&mstp7_clks R8A7790_CLK_LVDS0>,
		<&mstp7_clks R8A7790_CLK_LVDS1>;
		clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
		status = "disabled";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		du_out_rgb: endpoint {
		};
		};
		port@1 {
		reg = <1>;
		du_out_lvds0: endpoint {
		};
		};
		port@2 {
		reg = <2>;
		du_out_lvds1: endpoint {
		};
		};
		};
		};

		clocks {
		#address-cells = <2>;
		#size-cells = <2>;

arch/arm/boot/dts/r8a7791-koelsch.dts

+13 −3

Original line number	Diff line number	Diff line
		@@ -211,14 +211,24 @@
		};
		};

		&du {
		pinctrl-0 = <&du_pins>;
		pinctrl-names = "default";
		status = "okay";

		ports {
		port@1 {
		lvds_connector: endpoint {
		};
		};
		};
		};

		&extal_clk {
		clock-frequency = <20000000>;
		};

		&pfc {
		pinctrl-0 = <&du_pins>;
		pinctrl-names = "default";

		i2c2_pins: i2c2 {
		renesas,groups = "i2c2";
		renesas,function = "i2c2";