Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a2127e40 authored by Aleksey Makarov's avatar Aleksey Makarov Committed by Tejun Heo
Browse files

libata: support AHCI on OCTEON platform 



The OCTEON SATA controller is currently found on cn71XX devices.

Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Acked-by: default avatarHans de Goede <hdegoede@redhat.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
Signed-off-by: default avatarVinita Gupta <vgupta@caviumnetworks.com>
Signed-off-by: default avatarAleksey Makarov <aleksey.makarov@auriga.com>
Signed-off-by: default avatarZubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Signed-off-by: default avatarTejun Heo <tj@kernel.org>
parent 287e6611

Documentation/devicetree/bindings/ata/ahci-platform.txt

+1 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ Required properties: 
- compatible        : compatible string, one of:

  - "allwinner,sun4i-a10-ahci"

  - "hisilicon,hisi-ahci"

  - "cavium,octeon-7130-ahci"

  - "ibm,476gtr-ahci"

  - "marvell,armada-380-ahci"

  - "snps,dwc-ahci"

Documentation/devicetree/bindings/mips/cavium/sata-uctl.txt

0 → 100644
+42 −0
Original line number Diff line number Diff line 
* UCTL SATA controller glue



UCTL is the bridge unit between the I/O interconnect (an internal bus)

and the SATA AHCI host controller (UAHC). It performs the following functions:

	- provides interfaces for the applications to access the UAHC AHCI

	  registers on the CN71XX I/O space.

	- provides a bridge for UAHC to fetch AHCI command table entries and data

	  buffers from Level 2 Cache.

	- posts interrupts to the CIU.

	- contains registers that:

		- control the behavior of the UAHC

		- control the clock/reset generation to UAHC

		- control endian swapping for all UAHC registers and DMA accesses



Properties:



- compatible: "cavium,octeon-7130-sata-uctl"



  Compatibility with the cn7130 SOC.



- reg: The base address of the UCTL register bank.



- #address-cells, #size-cells, ranges and dma-ranges must be present and hold

	suitable values to map all child nodes.



Example:



	uctl@118006c000000 {

		compatible = "cavium,octeon-7130-sata-uctl";

		reg = <0x11800 0x6c000000 0x0 0x100>;

		ranges; /* Direct mapping */

		dma-ranges;

		#address-cells = <2>;

		#size-cells = <2>;



		sata: sata@16c0000000000 {

			compatible = "cavium,octeon-7130-ahci";

			reg = <0x16c00 0x00000000 0x0 0x200>;

			interrupt-parent = <&cibsata>;

			interrupts = <2 4>; /* Bit: 2, level */

		};

	};

arch/mips/include/asm/octeon/cvmx.h

+9 −0
Original line number Diff line number Diff line
@@ -275,6 +275,11 @@ static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val) 
		cvmx_read64(CVMX_MIO_BOOT_BIST_STAT);

}



static inline void cvmx_writeq_csr(void __iomem *csr_addr, uint64_t val)

{

	cvmx_write_csr((__force uint64_t)csr_addr, val);

}



static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)

{

	cvmx_write64(io_addr, val);
@@ -287,6 +292,10 @@ static inline uint64_t cvmx_read_csr(uint64_t csr_addr) 
	return val;

}



static inline uint64_t cvmx_readq_csr(void __iomem *csr_addr)

{

	return cvmx_read_csr((__force uint64_t) csr_addr);

}



static inline void cvmx_send_single(uint64_t data)

{

drivers/ata/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -151,6 +151,15 @@ config AHCI_MVEBU 


	  If unsure, say N.



config AHCI_OCTEON

	tristate "Cavium Octeon Soc Serial ATA"

	depends on SATA_AHCI_PLATFORM && CAVIUM_OCTEON_SOC

	default y

	help

	  This option enables support for Cavium Octeon SoC Serial ATA.



	  If unsure, say N.



config AHCI_SUNXI

	tristate "Allwinner sunxi AHCI SATA support"

	depends on ARCH_SUNXI

drivers/ata/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ obj-$(CONFIG_AHCI_CEVA) += ahci_ceva.o libahci.o libahci_platform.o 
obj-$(CONFIG_AHCI_DA850)	+= ahci_da850.o libahci.o libahci_platform.o

obj-$(CONFIG_AHCI_IMX)		+= ahci_imx.o libahci.o libahci_platform.o

obj-$(CONFIG_AHCI_MVEBU)	+= ahci_mvebu.o libahci.o libahci_platform.o

obj-$(CONFIG_AHCI_OCTEON)	+= ahci_octeon.o

obj-$(CONFIG_AHCI_SUNXI)	+= ahci_sunxi.o libahci.o libahci_platform.o

obj-$(CONFIG_AHCI_ST)		+= ahci_st.o libahci.o libahci_platform.o

obj-$(CONFIG_AHCI_TEGRA)	+= ahci_tegra.o libahci.o libahci_platform.o