Merge "bindings: clock: Add support of cpucc for QM215"

Qualcomm Technologies, Inc. MSM8939 CPU clock tree

clock-cpu-8939 is a device that represents the MSM8939 or MSM8952 CPU

subsystem clock tree. It lists the various power supplies that need to be

scaled when the clocks are scaled and also other HW specific parameters like

fmax tables, avs settings table, etc.

Required properties:

- compatible:		Must be one of "qcom,clock-cpu-8939" or

			"qcom,cpu-clock-8952", "qcom,cpu-clock-8917",

			"qcom,cpu-clock-sdm439", "qcom,cpu-clock-sdm429".

- reg:			Pairs of physical base addresses and region sizes of

			memory mapped registers.

- reg-names:		Names of the bases for the above registers. Expected

			bases are:

			"apcs-c0-rcg-base", "apcs-c1-rcg-base",

			"apcs-cci-rcg-base", "efuse", "efuse1", "efuse2"

- vdd-c0-supply:	The regulator powering the little cluster

- vdd-c1-supply:	The regulator powering the big cluster

- vdd-cci-supply:	The regulator powering the CCI cluster

- qcom,speedX-bin-vY-ZZZ:

			A table of CPU frequency (Hz) to voltage (corner)

			mapping that represents the max frequency possible

			for each supported voltage level for a CPU. 'X' is

			the speed bin into which the device falls into - a

			bin will have unique frequency-voltage relationships.

			'Y' is the characterization version, implying that

			characterization (deciding what speed bin a device

			falls into) methods and/or encoding may change. The

			values 'X' and 'Y' are read from efuse registers, and

			the right table is picked from multiple possible tables.

			'ZZZ' can be c1, c0 or cci depending on whether the table

			is for the big cluster, little cluster or cci.

Optional properties:

- qcom,cpu-pcnoc-vote:  Boolean to indicate cpu clocks would need to keep

			active pcnoc vote.

- qcom,num-cluster:     Boolean to indicate cpu clock code is used for single

			cluster.

Example:

	clock_cpu: qcom,cpu-clock-8939@f9015000 {

		compatible = "qcom,cpu-clock-8939";

		reg = <0xf9015000 0x1000>,

		      <0xf9016000 0x1000>,

		      <0xf9011000 0x1000>,

		      <0xf900d000 0x1000>,

		      <0xf900f000 0x1000>,

		      <0xf9112000 0x1000>;

		reg-names = "apcs-c0-rcg-base", "apcs-c1-rcg-base",

			     "apcs-cci-rcg-base", "efuse", "efuse1",

				"efuse2";

                vdd-c0-supply = <&apc_vreg_corner>;

		vdd-c1-supply = <&apc_vreg_corner>;

		vdd-cci-supply = <&apc_vreg_corner>;

		qcom,speed0-bin-v0-c0 =

			<         0 0>,

			< 384000000 1>,

			< 787200000 2>,

			<1286400000 3>;

		qcom,speed0-bin-v0-c1 =

			<         0 0>,

			< 384000000 1>,

			< 787200000 2>,

			<1785600000 3>;

		qcom,speed0-bin-v0-cci =

			<         0 0>,

			< 150000000 1>,

			< 300000000 2>,

			< 600000000 3>;

		clocks = <&clock_gcc clk_gpll0_ao>,

			<&clock_gcc clk_a53ss_c0_pll>,

			<&clock_gcc clk_gpll0_ao>,

			<&clock_gcc clk_a53ss_c1_pll>,

			<&clock_gcc clk_gpll0_ao>,

			<&clock_gcc clk_a53ss_cci_pll>;

			clock-names = "clk-c0-4", "clk-c0-5",

			"clk-c1-4", "clk-c1-5",

			"clk-cci-4", "clk-cci-5";

		#clock-cells = <1>;

};

Qualcomm Technologies, Inc. SDM CPU clock driver

---------------------------------------------------

It is the clock controller driver which provides higher frequency

clocks and allows CPU frequency scaling on sdm based platforms.

Required properties:

- compatible:	Shall contain following:

		"qcom,cpu-clock-sdm", "qcom,cpu-clock-qm215",

		"qcom,cpu-clock-sdm439", "qcom,cpu-clock-sdm429"

- clocks:	Phandle to the clock device.

- clock-names:	Names of the used clocks. Shall contain following:

		"xo_ao", "gpll0_ao"

- reg:	Shall contain base register offset and size.

- reg-names:	Names of the bases for the above registers. Shall contain following:

		"apcs-c1-rcg-base", "apcs-cci-rcg-base", "apcs_pll", "efuse"

- vdd_dig_ao-supply:	The regulator(active only) powering the digital logic of APSS PLL.

- vdd_hf_pll-supply:	The regulator(active only) powering the Analog logic of APSS PLL.

- cpu-vdd-supply:	The regulator powering the APSS C1 RCG and APSS CCI RCG.

- qcom,speedX-bin-vY-Z:	A table of CPU frequency (Hz) to regulator voltage (uV) mapping.

			Format: <freq uV>

			This represents the max frequency possible for each possible

			power configuration for a CPU that's binned as speed bin X,

			speed bin revision Y. Version can be between [0-3]. Z

			is the mux id c1 or cci.

- #clock-cells:	Shall contain 1.

Example:

	clock_cpu: qcom,clock-cpu@0b011050 {

		compatible = "qcom,cpu-clock-sdm";

		clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,

			<&gcc GPLL0_AO_OUT_MAIN>;

		clock-names = "xo_ao", "gpll0_ao" ;

		reg =   <0xb011050 0x8>,

			<0xb1d1050 0x8>,

			<0xb016000 0x34>,

			<0x00a412c 0x8>;

		reg-names = "apcs-c1-rcg-base",

			"apcs-cci-rcg-base", "apcs_pll", "efuse";

		cpu-vdd-supply = <&apc_vreg_corner>;

		vdd_dig_ao-supply = <&L12A_AO;

		vdd_hf_pll-supply = <&VDD_CX_LEVEL_AO>;

		qcom,speed0-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>,

			< 1958400000 5>;

		qcom,speed0-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;

		qcom,speed1-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>,

			< 1804800000 5>;

		qcom,speed1-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;

		qcom,speed4-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>,

			< 1958400000 5>,

			< 2016000000 6>;

		qcom,speed4-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;

		qcom,speed5-bin-v0-c1 =

			<          0 0>,

			<  960000000 1>,

			< 1305600000 1>,

			< 1497600000 2>,

			< 1708800000 3>;

		qcom,speed5-bin-v0-cci =

			<          0 0>,

			<  400000000 1>,

			<  533333333 3>;

		#clock-cells = <1>;

	};