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Commit a1f34af0 authored by Jiri Prchal's avatar Jiri Prchal Committed by Mark Brown
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ASoC: tlv320aic3x: add input clock selection 



This patch adds input selection of main codec clock - from what pin.
Both registers set same value since codec uses clock divider or pll at one time.

Signed-off-by: default avatarJiri Prchal <jiri.prchal@aksignal.cz>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent bb1daa80

sound/soc/codecs/tlv320aic3x.c

+6 −0
Original line number Diff line number Diff line
@@ -1002,6 +1002,12 @@ static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai, 
	struct snd_soc_codec *codec = codec_dai->codec;

	struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);



	/* set clock on MCLK or GPIO2 or BCLK */

	snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,

				clk_id << PLLCLK_IN_SHIFT);

	snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,

				clk_id << CLKDIV_IN_SHIFT);



	aic3x->sysclk = freq;

	return 0;

}

sound/soc/codecs/tlv320aic3x.h

+8 −0
Original line number Diff line number Diff line
@@ -195,6 +195,14 @@ 
#define PLL_CLKIN_SHIFT		4

#define MCLK_SOURCE		0x0

#define PLL_CLKDIV_SHIFT	0

#define PLLCLK_IN_MASK		0x30

#define PLLCLK_IN_SHIFT		4

#define CLKDIV_IN_MASK		0xc0

#define CLKDIV_IN_SHIFT		6

/* clock in source */

#define CLKIN_MCLK		0

#define CLKIN_GPIO2		1

#define CLKIN_BCLK		2



/* Software reset register bits */

#define SOFT_RESET		0x80