Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal

			    - "renesas,thermal-r8a73a4" (R-Mobile AP6)

			    - "renesas,thermal-r8a7779" (R-Car H1)

			    - "renesas,thermal-r8a7790" (R-Car H2)

			    - "renesas,thermal-r8a7791" (R-Car M2)

			    - "renesas,thermal-r8a7791" (R-Car M2-W)

			    - "renesas,thermal-r8a7792" (R-Car V2H)

			    - "renesas,thermal-r8a7793" (R-Car M2-N)

			    - "renesas,thermal-r8a7794" (R-Car E2)

- reg			: Address range of the thermal registers.

			  The 1st reg will be recognized as common register

			  if it has "interrupts".

				int (*get_trend)(void *, long *))

{

	struct device_node *np, *child, *sensor_np;

	struct thermal_zone_device *tzd = ERR_PTR(-ENODEV);

	np = of_find_node_by_name(NULL, "thermal-zones");

	if (!np)

		return ERR_PTR(-ENODEV);

	if (!dev || !dev->of_node)

	if (!dev || !dev->of_node) {

		of_node_put(np);

		return ERR_PTR(-EINVAL);

	}

	sensor_np = dev->of_node;

	sensor_np = of_node_get(dev->of_node);

	for_each_child_of_node(np, child) {

		struct of_phandle_args sensor_specs;

		}

		if (sensor_specs.np == sensor_np && id == sensor_id) {

			of_node_put(np);

			return thermal_zone_of_add_sensor(child, sensor_np,

			tzd = thermal_zone_of_add_sensor(child, sensor_np,

							 data,

							 get_temp,

							 get_trend);

			of_node_put(sensor_specs.np);

			of_node_put(child);

			goto exit;

		}

		of_node_put(sensor_specs.np);

	}

exit:

	of_node_put(sensor_np);

	of_node_put(np);

	return ERR_PTR(-ENODEV);

	return tzd;

}

EXPORT_SYMBOL_GPL(thermal_zone_of_sensor_register);

	/* Required for cooling map matching */

	trip->np = np;

	of_node_get(np);

	return 0;

}

	return tz;

free_tbps:

	for (i = 0; i < tz->num_tbps; i++)

		of_node_put(tz->tbps[i].cooling_device);

	kfree(tz->tbps);

free_trips:

	for (i = 0; i < tz->ntrips; i++)

		of_node_put(tz->trips[i].np);

	kfree(tz->trips);

	of_node_put(gchild);

free_tz:

	kfree(tz);

	of_node_put(child);

static inline void of_thermal_free_zone(struct __thermal_zone *tz)

{

	int i;

	for (i = 0; i < tz->num_tbps; i++)

		of_node_put(tz->tbps[i].cooling_device);

	kfree(tz->tbps);

	for (i = 0; i < tz->ntrips; i++)

		of_node_put(tz->trips[i].np);

	kfree(tz->trips);

	kfree(tz);

}

			/* attempting to build remaining zones still */

		}

	}

	of_node_put(np);

	return 0;

exit_free:

	of_node_put(child);

	of_node_put(np);

	of_thermal_free_zone(tz);

	/* no memory available, so free what we have built */

		kfree(zone->ops);

		of_thermal_free_zone(zone->devdata);

	}

	of_node_put(np);

}

#define SENSOR_NAME_LEN	16

#define MAX_TRIP_COUNT	8

#define MAX_COOLING_DEVICE 4

#define MAX_THRESHOLD_LEVS 5

#define MAX_TRIMINFO_CTRL_REG	2

#define ACTIVE_INTERVAL 500

#define IDLE_INTERVAL 10000

	struct exynos_tmu_platform_data *pdata = data->pdata;

	int temp_code;

	if (pdata->cal_mode == HW_MODE)

		return temp;

	if (data->soc == SOC_ARCH_EXYNOS4210)

		/* temp should range between 25 and 125 */

		if (temp < 25 || temp > 125) {

			temp_code = -EINVAL;

			goto out;

		}

	switch (pdata->cal_type) {

	case TYPE_TWO_POINT_TRIMMING:

		temp_code = (temp - pdata->first_point_trim) *

		temp_code = temp + pdata->default_temp_offset;

		break;

	}

out:

	return temp_code;

}

	struct exynos_tmu_platform_data *pdata = data->pdata;

	int temp;

	if (pdata->cal_mode == HW_MODE)

		return temp_code;

	if (data->soc == SOC_ARCH_EXYNOS4210)

		/* temp_code should range between 75 and 175 */

		if (temp_code < 75 || temp_code > 175) {

			temp = -ENODATA;

			goto out;

		}

	switch (pdata->cal_type) {

	case TYPE_TWO_POINT_TRIMMING:

		temp = (temp_code - data->temp_error1) *

		temp = temp_code - pdata->default_temp_offset;

		break;

	}

out:

	return temp;

}

static void exynos_tmu_clear_irqs(struct exynos_tmu_data *data)

{

	const struct exynos_tmu_registers *reg = data->pdata->registers;

	unsigned int val_irq;

	val_irq = readl(data->base + reg->tmu_intstat);

	/*

	 * Clear the interrupts.  Please note that the documentation for

	 * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly

	 * states that INTCLEAR register has a different placing of bits

	 * responsible for FALL IRQs than INTSTAT register.  Exynos5420

	 * and Exynos5440 documentation is correct (Exynos4210 doesn't

	 * support FALL IRQs at all).

	 */

	writel(val_irq, data->base + reg->tmu_intclear);

}

static int exynos_tmu_initialize(struct platform_device *pdev)

{

	struct exynos_tmu_data *data = platform_get_drvdata(pdev);

	struct exynos_tmu_platform_data *pdata = data->pdata;

	const struct exynos_tmu_registers *reg = pdata->registers;

	unsigned int status, trim_info = 0, con;

	unsigned int status, trim_info = 0, con, ctrl;

	unsigned int rising_threshold = 0, falling_threshold = 0;

	int ret = 0, threshold_code, i, trigger_levs = 0;

	int ret = 0, threshold_code, i;

	mutex_lock(&data->lock);

	clk_enable(data->clk);

		}

	}

	if (TMU_SUPPORTS(pdata, TRIM_RELOAD))

		__raw_writel(1, data->base + reg->triminfo_ctrl);

	if (pdata->cal_mode == HW_MODE)

		goto skip_calib_data;

	if (TMU_SUPPORTS(pdata, TRIM_RELOAD)) {

		for (i = 0; i < reg->triminfo_ctrl_count; i++) {

			if (pdata->triminfo_reload[i]) {

				ctrl = readl(data->base +

						reg->triminfo_ctrl[i]);

				ctrl |= pdata->triminfo_reload[i];

				writel(ctrl, data->base +

						reg->triminfo_ctrl[i]);

			}

		}

	}

	/* Save trimming info in order to perform calibration */

	if (data->soc == SOC_ARCH_EXYNOS5440) {

			trim_info = readl(data->base + reg->triminfo_data);

	}

	data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;

	data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &

	data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &

				EXYNOS_TMU_TEMP_MASK);

	if (!data->temp_error1 ||

	if (!data->temp_error2)

		data->temp_error2 =

			(pdata->efuse_value >> reg->triminfo_85_shift) &

			(pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &

			EXYNOS_TMU_TEMP_MASK;

skip_calib_data:

	if (pdata->max_trigger_level > MAX_THRESHOLD_LEVS) {

		dev_err(&pdev->dev, "Invalid max trigger level\n");

		ret = -EINVAL;

		goto out;

	}

	for (i = 0; i < pdata->max_trigger_level; i++) {

		if (!pdata->trigger_levels[i])

			continue;

		if ((pdata->trigger_type[i] == HW_TRIP) &&

		(!pdata->trigger_levels[pdata->max_trigger_level - 1])) {

			dev_err(&pdev->dev, "Invalid hw trigger level\n");

			ret = -EINVAL;

			goto out;

		}

		/* Count trigger levels except the HW trip*/

		if (!(pdata->trigger_type[i] == HW_TRIP))

			trigger_levs++;

	}

	rising_threshold = readl(data->base + reg->threshold_th0);

	if (data->soc == SOC_ARCH_EXYNOS4210) {

		/* Write temperature code for threshold */

		threshold_code = temp_to_code(data, pdata->threshold);

		if (threshold_code < 0) {

			ret = threshold_code;

			goto out;

		}

		writeb(threshold_code,

			data->base + reg->threshold_temp);

		for (i = 0; i < trigger_levs; i++)

		for (i = 0; i < pdata->non_hw_trigger_levels; i++)

			writeb(pdata->trigger_levels[i], data->base +

			reg->threshold_th0 + i * sizeof(reg->threshold_th0));

		writel(reg->intclr_rise_mask, data->base + reg->tmu_intclear);

		exynos_tmu_clear_irqs(data);

	} else {

		/* Write temperature code for rising and falling threshold */

		for (i = 0;

		i < trigger_levs && i < EXYNOS_MAX_TRIGGER_PER_REG; i++) {

		for (i = 0; i < pdata->non_hw_trigger_levels; i++) {

			threshold_code = temp_to_code(data,

						pdata->trigger_levels[i]);

			if (threshold_code < 0) {

				ret = threshold_code;

				goto out;

			}

			rising_threshold &= ~(0xff << 8 * i);

			rising_threshold |= threshold_code << 8 * i;

			if (pdata->threshold_falling) {

				threshold_code = temp_to_code(data,

						pdata->trigger_levels[i] -

						pdata->threshold_falling);

				if (threshold_code > 0)

					falling_threshold |=

						threshold_code << 8 * i;

				falling_threshold |= threshold_code << 8 * i;

			}

		}

		writel(falling_threshold,

				data->base + reg->threshold_th1);

		writel((reg->intclr_rise_mask << reg->intclr_rise_shift) |

			(reg->intclr_fall_mask << reg->intclr_fall_shift),

				data->base + reg->tmu_intclear);

		exynos_tmu_clear_irqs(data);

		/* if last threshold limit is also present */

		i = pdata->max_trigger_level - 1;

				(pdata->trigger_type[i] == HW_TRIP)) {

			threshold_code = temp_to_code(data,

						pdata->trigger_levels[i]);

			if (threshold_code < 0) {

				ret = threshold_code;

				goto out;

			}

			if (i == EXYNOS_MAX_TRIGGER_PER_REG - 1) {

				/* 1-4 level to be assigned in th0 reg */

				rising_threshold &= ~(0xff << 8 * i);

	struct exynos_tmu_data *data = platform_get_drvdata(pdev);

	struct exynos_tmu_platform_data *pdata = data->pdata;

	const struct exynos_tmu_registers *reg = pdata->registers;

	unsigned int con, interrupt_en, cal_val;

	unsigned int con, interrupt_en;

	mutex_lock(&data->lock);

	clk_enable(data->clk);

	if (pdata->test_mux)

		con |= (pdata->test_mux << reg->test_mux_addr_shift);

	if (pdata->reference_voltage) {

		con &= ~(reg->buf_vref_sel_mask << reg->buf_vref_sel_shift);

		con |= pdata->reference_voltage << reg->buf_vref_sel_shift;

	}

	con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT);

	con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;

	if (pdata->gain) {

		con &= ~(reg->buf_slope_sel_mask << reg->buf_slope_sel_shift);

		con |= (pdata->gain << reg->buf_slope_sel_shift);

	}

	con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);

	con |= (pdata->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);

	if (pdata->noise_cancel_mode) {

		con &= ~(reg->therm_trip_mode_mask <<

		con |= (pdata->noise_cancel_mode << reg->therm_trip_mode_shift);

	}

	if (pdata->cal_mode == HW_MODE) {

		con &= ~(reg->calib_mode_mask << reg->calib_mode_shift);

		cal_val = 0;

		switch (pdata->cal_type) {

		case TYPE_TWO_POINT_TRIMMING:

			cal_val = 3;

			break;

		case TYPE_ONE_POINT_TRIMMING_85:

			cal_val = 2;

			break;

		case TYPE_ONE_POINT_TRIMMING_25:

			cal_val = 1;

			break;

		case TYPE_NONE:

			break;

		default:

			dev_err(&pdev->dev, "Invalid calibration type, using none\n");

		}

		con |= cal_val << reg->calib_mode_shift;

	}

	if (on) {

		con |= (1 << reg->core_en_shift);

		con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);

		interrupt_en =

			pdata->trigger_enable[3] << reg->inten_rise3_shift |

			pdata->trigger_enable[2] << reg->inten_rise2_shift |

			interrupt_en |=

				interrupt_en << reg->inten_fall0_shift;

	} else {

		con &= ~(1 << reg->core_en_shift);

		con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);

		interrupt_en = 0; /* Disable all interrupts */

	}

	writel(interrupt_en, data->base + reg->tmu_inten);

	clk_enable(data->clk);

	temp_code = readb(data->base + reg->tmu_cur_temp);

	temp = code_to_temp(data, temp_code);

	if (data->soc == SOC_ARCH_EXYNOS4210)

		/* temp_code should range between 75 and 175 */

		if (temp_code < 75 || temp_code > 175) {

			temp = -ENODATA;

			goto out;

		}

	temp = code_to_temp(data, temp_code);

out:

	clk_disable(data->clk);

	mutex_unlock(&data->lock);

			struct exynos_tmu_data, irq_work);

	struct exynos_tmu_platform_data *pdata = data->pdata;

	const struct exynos_tmu_registers *reg = pdata->registers;

	unsigned int val_irq, val_type;

	unsigned int val_type;

	if (!IS_ERR(data->clk_sec))

		clk_enable(data->clk_sec);

	clk_enable(data->clk);

	/* TODO: take action based on particular interrupt */

	val_irq = readl(data->base + reg->tmu_intstat);

	/* clear the interrupts */

	writel(val_irq, data->base + reg->tmu_intclear);

	exynos_tmu_clear_irqs(data);

	clk_disable(data->clk);

	mutex_unlock(&data->lock);

	TYPE_NONE,

};

enum calibration_mode {

	SW_MODE,

	HW_MODE,

};

enum soc_type {

	SOC_ARCH_EXYNOS3250 = 1,

	SOC_ARCH_EXYNOS4210,

 * bitfields. The register validity, offsets and bitfield values may vary

 * slightly across different exynos SOC's.

 * @triminfo_data: register containing 2 pont trimming data

 * @triminfo_25_shift: shift bit of the 25 C trim value in triminfo_data reg.

 * @triminfo_85_shift: shift bit of the 85 C trim value in triminfo_data reg.

 * @triminfo_ctrl: trim info controller register.

 * @triminfo_reload_shift: shift of triminfo reload enable bit in triminfo_ctrl

	reg.

 * @triminfo_ctrl_count: the number of trim info controller register.

 * @tmu_ctrl: TMU main controller register.

 * @test_mux_addr_shift: shift bits of test mux address.

 * @buf_vref_sel_shift: shift bits of reference voltage in tmu_ctrl register.

 * @buf_vref_sel_mask: mask bits of reference voltage in tmu_ctrl register.

 * @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register.

 * @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register.

 * @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register.

 * @buf_slope_sel_shift: shift bits of amplifier gain value in tmu_ctrl

	register.

 * @buf_slope_sel_mask: mask bits of amplifier gain value in tmu_ctrl register.

 * @calib_mode_shift: shift bits of calibration mode value in tmu_ctrl

	register.

 * @calib_mode_mask: mask bits of calibration mode value in tmu_ctrl

	register.

 * @therm_trip_tq_en_shift: shift bits of thermal trip enable by TQ pin in

	tmu_ctrl register.

 * @core_en_shift: shift bits of TMU core enable bit in tmu_ctrl register.

 * @tmu_status: register drescribing the TMU status.

 * @tmu_cur_temp: register containing the current temperature of the TMU.

 * @tmu_cur_temp_shift: shift bits of current temp value in tmu_cur_temp

	register.

 * @threshold_temp: register containing the base threshold level.

 * @threshold_th0: Register containing first set of rising levels.

 * @threshold_th0_l0_shift: shift bits of level0 threshold temperature.

 * @threshold_th0_l1_shift: shift bits of level1 threshold temperature.

 * @threshold_th0_l2_shift: shift bits of level2 threshold temperature.

 * @threshold_th0_l3_shift: shift bits of level3 threshold temperature.

 * @threshold_th1: Register containing second set of rising levels.

 * @threshold_th1_l0_shift: shift bits of level0 threshold temperature.

 * @threshold_th1_l1_shift: shift bits of level1 threshold temperature.

 * @threshold_th1_l2_shift: shift bits of level2 threshold temperature.

 * @threshold_th1_l3_shift: shift bits of level3 threshold temperature.

 * @threshold_th2: Register containing third set of rising levels.

 * @threshold_th2_l0_shift: shift bits of level0 threshold temperature.

 * @threshold_th3: Register containing fourth set of rising levels.

 * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.

 * @tmu_inten: register containing the different threshold interrupt

	enable bits.

 * @inten_rise2_shift: shift bits of rising 2 interrupt bits.

 * @inten_rise3_shift: shift bits of rising 3 interrupt bits.

 * @inten_fall0_shift: shift bits of falling 0 interrupt bits.

 * @inten_fall1_shift: shift bits of falling 1 interrupt bits.

 * @inten_fall2_shift: shift bits of falling 2 interrupt bits.

 * @inten_fall3_shift: shift bits of falling 3 interrupt bits.

 * @tmu_intstat: Register containing the interrupt status values.

 * @tmu_intclear: Register for clearing the raised interrupt status.

 * @intclr_fall_shift: shift bits for interrupt clear fall 0

 * @intclr_rise_shift: shift bits of all rising interrupt bits.

 * @intclr_rise_mask: mask bits of all rising interrupt bits.

 * @intclr_fall_mask: mask bits of all rising interrupt bits.

 * @emul_con: TMU emulation controller register.

 * @emul_temp_shift: shift bits of emulation temperature.

 * @emul_time_shift: shift bits of emulation time.

 * @emul_time_mask: mask bits of emulation time.

 * @tmu_irqstatus: register to find which TMU generated interrupts.

 * @tmu_pmin: register to get/set the Pmin value.

 */

struct exynos_tmu_registers {

	u32	triminfo_data;

	u32	triminfo_25_shift;

	u32	triminfo_85_shift;

	u32	triminfo_ctrl;

	u32	triminfo_ctrl1;

	u32	triminfo_reload_shift;

	u32	triminfo_ctrl[MAX_TRIMINFO_CTRL_REG];

	u32	triminfo_ctrl_count;

	u32	tmu_ctrl;

	u32     test_mux_addr_shift;

	u32	buf_vref_sel_shift;

	u32	buf_vref_sel_mask;

	u32	therm_trip_mode_shift;

	u32	therm_trip_mode_mask;

	u32	therm_trip_en_shift;

	u32	buf_slope_sel_shift;

	u32	buf_slope_sel_mask;

	u32	calib_mode_shift;

	u32	calib_mode_mask;

	u32	therm_trip_tq_en_shift;

	u32	core_en_shift;

	u32	tmu_status;

	u32	tmu_cur_temp;

	u32	tmu_cur_temp_shift;

	u32	threshold_temp;

	u32	threshold_th0;

	u32	threshold_th0_l0_shift;

	u32	threshold_th0_l1_shift;

	u32	threshold_th0_l2_shift;

	u32	threshold_th0_l3_shift;

	u32	threshold_th1;

	u32	threshold_th1_l0_shift;

	u32	threshold_th1_l1_shift;

	u32	threshold_th1_l2_shift;

	u32	threshold_th1_l3_shift;

	u32	threshold_th2;

	u32	threshold_th2_l0_shift;

	u32	threshold_th3;

	u32	threshold_th3_l0_shift;

	u32	tmu_inten;

	u32	inten_rise2_shift;

	u32	inten_rise3_shift;

	u32	inten_fall0_shift;

	u32	inten_fall1_shift;

	u32	inten_fall2_shift;

	u32	inten_fall3_shift;

	u32	tmu_intstat;

	u32	tmu_intclear;

	u32	intclr_fall_shift;

	u32	intclr_rise_shift;

	u32	intclr_fall_mask;

	u32	intclr_rise_mask;

	u32	emul_con;

	u32	emul_temp_shift;

	u32	emul_time_shift;

	u32	emul_time_mask;

	u32	tmu_irqstatus;

	u32	tmu_pmin;

 *	1 = enable trigger_level[] interrupt,

 *	0 = disable trigger_level[] interrupt

 * @max_trigger_level: max trigger level supported by the TMU

 * @non_hw_trigger_levels: number of defined non-hardware trigger levels

 * @gain: gain of amplifier in the positive-TC generator block

 *	0 <= gain <= 15

 *	0 < gain <= 15

 * @reference_voltage: reference voltage of amplifier

 *	in the positive-TC generator block

 *	0 <= reference_voltage <= 31

 *	0 < reference_voltage <= 31

 * @noise_cancel_mode: noise cancellation mode

 *	000, 100, 101, 110 and 111 can be different modes

 * @type: determines the type of SOC

 * @second_point_trim: temp value of the second point trimming

 * @default_temp_offset: default temperature offset in case of no trimming

 * @test_mux; information if SoC supports test MUX

 * @triminfo_reload: reload value to read TRIMINFO register

 * @cal_type: calibration type for temperature

 * @cal_mode: calibration mode for temperature

 * @freq_clip_table: Table representing frequency reduction percentage.

 * @freq_tab_count: Count of the above table as frequency reduction may

 *	applicable to only some of the trigger levels.

	enum trigger_type trigger_type[MAX_TRIP_COUNT];

	bool trigger_enable[MAX_TRIP_COUNT];

	u8 max_trigger_level;

	u8 non_hw_trigger_levels;

	u8 gain;

	u8 reference_voltage;

	u8 noise_cancel_mode;

	u8 second_point_trim;

	u8 default_temp_offset;

	u8 test_mux;

	u8 triminfo_reload[MAX_TRIMINFO_CTRL_REG];

	enum calibration_type cal_type;

	enum calibration_mode cal_mode;

	enum soc_type type;

	struct freq_clip_table freq_tab[4];

	unsigned int freq_tab_count;