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Commit a1a30f89 authored by Andrey Smirnov's avatar Andrey Smirnov Committed by Shawn Guo
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ARM: dts: imx51-zii-scu3-esb: Add switch IRQ line pinumx config 



Instead of relying on default values, configure PAD_AUD3_BB_CK to be a
GPIO explicitly. While at, it change the pad configuration to enable
a 100K pull-down (the pin is used as IRQ_TYPE_LEVEL_HIGH).

Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: cphealy@gmail.com
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarAndrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 2da6b9ce

arch/arm/boot/dts/imx51-zii-scu3-esb.dts

+8 −0
Original line number Diff line number Diff line
@@ -221,6 +221,8 @@ 
			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;

			#interrupt-cells = <2>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_switch>;



			ports {

				#address-cells = <1>;
@@ -426,6 +428,12 @@ 
		>;

	};



	pinctrl_switch: switchgrp {

		fsl,pins = <

			MX51_PAD_AUD3_BB_CK__GPIO4_20		0xc5

		>;

	};



	pinctrl_uart1: uart1grp {

		fsl,pins = <

			MX51_PAD_UART1_RXD__UART1_RXD		0x1c5