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Commit a186d25d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-for-v3.7-rc5' of... 

Merge tag 'pinctrl-for-v3.7-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pinctrl fixes from Linus Walleij:

 - A set of SPEAr pinctrl fixes that recently arrived

 - A fixup for the Samsung/Exynos Kconfig deps

* tag 'pinctrl-for-v3.7-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: samsung and exynos need to depend on OF && GPIOLIB
  pinctrl: SPEAr1340: Add clcd sleep mode pin configuration
  pinctrl: SPEAr1340: Make DDR reset & clock pads as gpio
  pinctrl: SPEAr1310: add register entries for enabling pad direction
  pinctrl: SPEAr1310: Separate out pci pins from pcie_sata pin group
  pinctrl: SPEAr1310: Fix value of PERIP_CFG reigster and MCIF_SEL_SHIFT
  pinctrl: SPEAr1310: fix clcd high resolution pin group name
  pinctrl: SPEAr320: Correct pad mux entries for rmii/smii
  pinctrl: SPEAr3xx: correct register space to configure pwm
  pinctrl: SPEAr: Don't update all non muxreg bits on pinctrl_disable
parents 4ad48bb7 924da314

drivers/pinctrl/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -179,11 +179,13 @@ config PINCTRL_COH901 


config PINCTRL_SAMSUNG

	bool "Samsung pinctrl driver"

	depends on OF && GPIOLIB

	select PINMUX

	select PINCONF



config PINCTRL_EXYNOS4

	bool "Pinctrl driver data for Exynos4 SoC"

	depends on OF && GPIOLIB

	select PINCTRL_SAMSUNG



config PINCTRL_MVEBU

drivers/pinctrl/spear/pinctrl-spear.c

+1 −1
Original line number Diff line number Diff line
@@ -244,7 +244,7 @@ static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev, 
			else

				temp = ~muxreg->val;



			val |= temp;

			val |= muxreg->mask & temp;

			pmx_writel(pmx, val, muxreg->reg);

		}

	}

drivers/pinctrl/spear/pinctrl-spear1310.c

+320 −45

File changed.

Preview size limit exceeded, changes collapsed.

drivers/pinctrl/spear/pinctrl-spear1340.c

+39 −2
Original line number Diff line number Diff line
@@ -213,7 +213,7 @@ static const struct pinctrl_pin_desc spear1340_pins[] = { 
 * Pad multiplexing for making all pads as gpio's. This is done to override the

 * values passed from bootloader and start from scratch.

 */

static const unsigned pads_as_gpio_pins[] = { 251 };

static const unsigned pads_as_gpio_pins[] = { 12, 88, 89, 251 };

static struct spear_muxreg pads_as_gpio_muxreg[] = {

	{

		.reg = PAD_FUNCTION_EN_1,
@@ -1692,7 +1692,43 @@ static struct spear_pingroup clcd_pingroup = { 
	.nmodemuxs = ARRAY_SIZE(clcd_modemux),

};



static const char *const clcd_grps[] = { "clcd_grp" };

/* Disable cld runtime to save panel damage */

static struct spear_muxreg clcd_sleep_muxreg[] = {

	{

		.reg = PAD_SHARED_IP_EN_1,

		.mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,

		.val = 0,

	}, {

		.reg = PAD_FUNCTION_EN_5,

		.mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,

		.val = 0x0,

	}, {

		.reg = PAD_FUNCTION_EN_6,

		.mask = CLCD_AND_ARM_TRACE_REG5_MASK,

		.val = 0x0,

	}, {

		.reg = PAD_FUNCTION_EN_7,

		.mask = CLCD_AND_ARM_TRACE_REG6_MASK,

		.val = 0x0,

	},

};



static struct spear_modemux clcd_sleep_modemux[] = {

	{

		.muxregs = clcd_sleep_muxreg,

		.nmuxregs = ARRAY_SIZE(clcd_sleep_muxreg),

	},

};



static struct spear_pingroup clcd_sleep_pingroup = {

	.name = "clcd_sleep_grp",

	.pins = clcd_pins,

	.npins = ARRAY_SIZE(clcd_pins),

	.modemuxs = clcd_sleep_modemux,

	.nmodemuxs = ARRAY_SIZE(clcd_sleep_modemux),

};



static const char *const clcd_grps[] = { "clcd_grp", "clcd_sleep_grp" };

static struct spear_function clcd_function = {

	.name = "clcd",

	.groups = clcd_grps,
@@ -1893,6 +1929,7 @@ static struct spear_pingroup *spear1340_pingroups[] = { 
	&sdhci_pingroup,

	&cf_pingroup,

	&xd_pingroup,

	&clcd_sleep_pingroup,

	&clcd_pingroup,

	&arm_trace_pingroup,

	&miphy_dbg_pingroup,

drivers/pinctrl/spear/pinctrl-spear320.c

+6 −2
Original line number Diff line number Diff line
@@ -2239,6 +2239,10 @@ static struct spear_muxreg pwm2_pin_34_muxreg[] = { 
		.reg = PMX_CONFIG_REG,

		.mask = PMX_SSP_CS_MASK,

		.val = 0,

	}, {

		.reg = MODE_CONFIG_REG,

		.mask = PMX_PWM_MASK,

		.val = PMX_PWM_MASK,

	}, {

		.reg = IP_SEL_PAD_30_39_REG,

		.mask = PMX_PL_34_MASK,
@@ -2956,9 +2960,9 @@ static struct spear_function mii2_function = { 
};



/* Pad multiplexing for cadence mii 1_2 as smii or rmii device */

static const unsigned smii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,

static const unsigned rmii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,

	21, 22, 23, 24, 25, 26, 27 };

static const unsigned rmii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 };

static const unsigned smii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 };

static struct spear_muxreg mii0_1_muxreg[] = {

	{

		.reg = PMX_CONFIG_REG,