Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a115f636 authored by ABE Hiroshige's avatar ABE Hiroshige Committed by Geert Uytterhoeven
Browse files

clk: renesas: r8a7796: Add FDP clock 



This patch adds FDP1-0 clock to the R8A7796 SoC.

Signed-off-by: default avatarABE Hiroshige <hiroshige.abe.zc@renesas.com>
Signed-off-by: default avatarTakeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: s/fdp0/fdp1-0/]
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
parent 7aff2665

drivers/clk/renesas/r8a7796-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -115,6 +115,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { 
};



static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {

	DEF_MOD("fdp1-0",		 119,	R8A7796_CLK_S0D1),

	DEF_MOD("scif5",		 202,	R8A7796_CLK_S3D4),

	DEF_MOD("scif4",		 203,	R8A7796_CLK_S3D4),

	DEF_MOD("scif3",		 204,	R8A7796_CLK_S3D4),