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Unverified Commit a07539c0 authored by Paul Burton's avatar Paul Burton
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MIPS: Malta: Cleanup DMA coherence #ifdefs 



DMA coherence is not user-selectable in Kconfig, and Malta selects
CONFIG_DMA_MAYBE_COHERENT which in turn selects CONFIG_DMA_NONCOHERENT.
Remove #ifdefs whose conditions can therefore never be true for Malta.

This removes a significant amount of code from bonito_quirks_setup(),
but the code is duplicated in plat_enable_iocoherency() anyway so we
lose nothing but duplication.

Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/14188/
parent d1c5872c

arch/mips/mti-malta/malta-setup.c

+0 −38
Original line number Diff line number Diff line
@@ -145,12 +145,6 @@ static int __init plat_enable_iocoherency(void) 


static void __init plat_setup_iocoherency(void)

{

#ifdef CONFIG_DMA_NONCOHERENT

	/*

	 * Kernel has been configured with software coherency

	 * but we might choose to turn it off and use hardware

	 * coherency instead.

	 */

	if (plat_enable_iocoherency()) {

		if (coherentio == IO_COHERENCE_DISABLED)

			pr_info("Hardware DMA cache coherency disabled\n");
@@ -162,10 +156,6 @@ static void __init plat_setup_iocoherency(void) 
		else

			pr_info("Software DMA cache coherency enabled\n");

	}

#else

	if (!plat_enable_iocoherency())

		panic("Hardware DMA cache coherency not supported!");

#endif

}



static void __init pci_clock_check(void)
@@ -227,29 +217,6 @@ static void __init bonito_quirks_setup(void) 
		pr_info("Enabled Bonito debug mode\n");

	} else

		BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;



#ifndef CONFIG_DMA_NONCOHERENT

	if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {

		BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;

		pr_info("Enabled Bonito CPU coherency\n");



		argptr = fw_getcmdline();

		if (strstr(argptr, "iobcuncached")) {

			BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;

			BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &

				~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |

					BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);

			pr_info("Disabled Bonito IOBC coherency\n");

		} else {

			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;

			BONITO_PCIMEMBASECFG |=

				(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |

					BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);

			pr_info("Enabled Bonito IOBC coherency\n");

		}

	} else

		panic("Hardware DMA cache coherency not supported");

#endif

}



void __init *plat_get_fdt(void)
@@ -280,11 +247,6 @@ void __init plat_mem_setup(void) 
	 */

	enable_dma(4);



#ifndef CONFIG_DMA_NONCOHERENT

	if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)

		panic("Hardware DMA cache coherency not supported");

#endif



	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)

		bonito_quirks_setup();