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Commit 9faf870e authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Ulf Hansson
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mmc: renesas_sdhi_internal_dmac: fix #define RST_RESERVED_BITS 



The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits
32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS.

Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Fixes: 2a68ea78 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC")
Cc: stable@vger.kernel.org # v4.14+
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 26caddf2

drivers/mmc/host/renesas_sdhi_internal_dmac.c

+1 −1
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ 
/* DM_CM_RST */

#define RST_DTRANRST1		BIT(9)

#define RST_DTRANRST0		BIT(8)

#define RST_RESERVED_BITS	GENMASK_ULL(32, 0)

#define RST_RESERVED_BITS	GENMASK_ULL(31, 0)



/* DM_CM_INFO1 and DM_CM_INFO1_MASK */

#define INFO1_CLEAR		0