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Commit 9fabd4ee authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel into drm-next 

Daniel writes:
Highlights of this -next round:
- ivb fdi B/C fixes
- hsw sprite/plane offset fixes from Damien
- unified dp/hdmi encoder for hsw, finally external dp support on hsw
  (Paulo)
- kill-agp and some other prep work in the gtt code from Ben
- some fb handling fixes from Ville
- massive pile of patches to align hsw VGA with the spec and make it
  actually work (Paulo)
- pile of workarounds from Jesse, mostly for vlv, but also some other
  related platforms
- start of a dev_priv reorg, that thing grew out of bounds and chaotic
- small bits&pieces all over the place, down to better error handling for
  load-detect on gen2 (Chris, Jani, Mika, Zhenyu, ...)

On top of the previous pile (just copypasta):
- tons of hsw dp prep patches form Paulo
- round scheduled work items and timers to nearest second (Chris)
- some hw workarounds (Jesse&Damien)
- vlv dp support and related fixups (Vijay et al.)
- basic haswell dp support, not yet wired up for external ports (Paulo)
- edp support (Paulo)
- tons of refactorings to prepare for the above (Paulo)
- panel rework, unifiying code between lvds and edp panels (Jani)
- panel fitter scaling modes (Jani + Yuly Novikov)
- panel power improvements, should now work without the BIOS setting it up
- extracting some dp helpers from radeon/i915 and move them to
  drm_dp_helper.c
- randome pile of workarounds (Damien, Ben, ...)
- some cleanups for the register restore code for suspend/resume
- secure batchbuffer support, should enable tear-free blits on gen6+
  Chris)
- random smaller fixlets and cleanups.

* 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel: (231 commits)
  drm/i915: Restore physical HWS_PGA after resume
  drm/i915: Report amount of usable graphics memory in MiB
  drm/i915/i2c: Track users of GMBUS force-bit
  drm/i915: Allocate the proper size for contexts.
  drm/i915: Update load-detect failure paths for modeset-rework
  drm/i915: Clear unused fields of mode for framebuffer creation
  drm/i915: Always calculate 8xx WM values based on a 32-bpp framebuffer
  drm/i915: Fix sparse warnings in from AGP kill code
  drm/i915: Missed lock change with rps lock
  drm/i915: Move the remaining gtt code
  drm/i915: flush system agent TLBs on SNB
  drm/i915: Kill off now unused gen6+ AGP code
  drm/i915: Calculate correct stolen size for GEN7+
  drm/i915: Stop using AGP layer for GEN6+
  drm/i915: drop the double-OP_STOREDW usage in blt_ring_flush
  drm/i915: don't rewrite the GTT on resume v4
  drm/i915: protect RPS/RC6 related accesses (including PCU) with a new mutex
  drm/i915: put ring frequency and turbo setup into a work queue v5
  drm/i915: don't block resume on fb console resume v2
  drm/i915: extract l3_parity substruct from dev_priv
  ...
parents 6380813c 6b8294a4

drivers/char/agp/intel-agp.h

+0 −91
Original line number Diff line number Diff line
@@ -62,12 +62,6 @@ 
#define I810_PTE_LOCAL		0x00000002

#define I810_PTE_VALID		0x00000001

#define I830_PTE_SYSTEM_CACHED  0x00000006

/* GT PTE cache control fields */

#define GEN6_PTE_UNCACHED	0x00000002

#define HSW_PTE_UNCACHED	0x00000000

#define GEN6_PTE_LLC		0x00000004

#define GEN6_PTE_LLC_MLC	0x00000006

#define GEN6_PTE_GFDT		0x00000008



#define I810_SMRAM_MISCC	0x70

#define I810_GFX_MEM_WIN_SIZE	0x00010000
@@ -97,7 +91,6 @@ 
#define G4x_GMCH_SIZE_VT_2M	(G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN)



#define GFX_FLSH_CNTL		0x2170 /* 915+ */

#define GFX_FLSH_CNTL_VLV	0x101008



#define I810_DRAM_CTL		0x3000

#define I810_DRAM_ROW_0		0x00000001
@@ -148,29 +141,6 @@ 
#define INTEL_I7505_AGPCTRL	0x70

#define INTEL_I7505_MCHCFG	0x50



#define SNB_GMCH_CTRL	0x50

#define SNB_GMCH_GMS_STOLEN_MASK	0xF8

#define SNB_GMCH_GMS_STOLEN_32M		(1 << 3)

#define SNB_GMCH_GMS_STOLEN_64M		(2 << 3)

#define SNB_GMCH_GMS_STOLEN_96M		(3 << 3)

#define SNB_GMCH_GMS_STOLEN_128M	(4 << 3)

#define SNB_GMCH_GMS_STOLEN_160M	(5 << 3)

#define SNB_GMCH_GMS_STOLEN_192M	(6 << 3)

#define SNB_GMCH_GMS_STOLEN_224M	(7 << 3)

#define SNB_GMCH_GMS_STOLEN_256M	(8 << 3)

#define SNB_GMCH_GMS_STOLEN_288M	(9 << 3)

#define SNB_GMCH_GMS_STOLEN_320M	(0xa << 3)

#define SNB_GMCH_GMS_STOLEN_352M	(0xb << 3)

#define SNB_GMCH_GMS_STOLEN_384M	(0xc << 3)

#define SNB_GMCH_GMS_STOLEN_416M	(0xd << 3)

#define SNB_GMCH_GMS_STOLEN_448M	(0xe << 3)

#define SNB_GMCH_GMS_STOLEN_480M	(0xf << 3)

#define SNB_GMCH_GMS_STOLEN_512M	(0x10 << 3)

#define SNB_GTT_SIZE_0M			(0 << 8)

#define SNB_GTT_SIZE_1M			(1 << 8)

#define SNB_GTT_SIZE_2M			(2 << 8)

#define SNB_GTT_SIZE_MASK		(3 << 8)



/* pci devices ids */

#define PCI_DEVICE_ID_INTEL_E7221_HB	0x2588

#define PCI_DEVICE_ID_INTEL_E7221_IG	0x258a
@@ -219,66 +189,5 @@ 
#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB	    0x0062

#define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB    0x006a

#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG	    0x0046

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB		0x0100  /* Desktop */

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG		0x0102

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG		0x0112

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG	0x0122

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB		0x0104  /* Mobile */

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG	0x0106

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG	0x0116

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG	0x0126

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB		0x0108  /* Server */

#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG		0x010A

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB		0x0150  /* Desktop */

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG		0x0152

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG		0x0162

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB		0x0154  /* Mobile */

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG		0x0156

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG		0x0166

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB		0x0158  /* Server */

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG		0x015A

#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG		0x016A

#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB		0x0F00 /* VLV1 */

#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG		0x0F30

#define PCI_DEVICE_ID_INTEL_HASWELL_HB			0x0400 /* Desktop */

#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG		0x0402

#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG		0x0412

#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG	0x0422

#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB		0x0404 /* Mobile */

#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG		0x0406

#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG		0x0416

#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG	0x0426

#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB		0x0408 /* Server */

#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG		0x040a

#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG		0x041a

#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG	0x042a

#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB		0x0c04

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG	0x0C02

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG	0x0C12

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG	0x0C22

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG	0x0C06

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG	0x0C16

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG	0x0C26

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG	0x0C0A

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG	0x0C1A

#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG	0x0C2A

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG	0x0A02

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG	0x0A12

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG	0x0A22

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG	0x0A06

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG	0x0A16

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG	0x0A26

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG	0x0A0A

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG	0x0A1A

#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG	0x0A2A

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG	0x0D12

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG	0x0D22

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG	0x0D32

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG	0x0D16

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG	0x0D26

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG	0x0D36

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG	0x0D1A

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG	0x0D2A

#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG	0x0D3A



#endif

drivers/char/agp/intel-gtt.c

+12 −308
Original line number Diff line number Diff line
@@ -367,62 +367,6 @@ static unsigned int intel_gtt_stolen_size(void) 
			stolen_size = 0;

			break;

		}

	} else if (INTEL_GTT_GEN == 6) {

		/*

		 * SandyBridge has new memory control reg at 0x50.w

		 */

		u16 snb_gmch_ctl;

		pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);

		switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {

		case SNB_GMCH_GMS_STOLEN_32M:

			stolen_size = MB(32);

			break;

		case SNB_GMCH_GMS_STOLEN_64M:

			stolen_size = MB(64);

			break;

		case SNB_GMCH_GMS_STOLEN_96M:

			stolen_size = MB(96);

			break;

		case SNB_GMCH_GMS_STOLEN_128M:

			stolen_size = MB(128);

			break;

		case SNB_GMCH_GMS_STOLEN_160M:

			stolen_size = MB(160);

			break;

		case SNB_GMCH_GMS_STOLEN_192M:

			stolen_size = MB(192);

			break;

		case SNB_GMCH_GMS_STOLEN_224M:

			stolen_size = MB(224);

			break;

		case SNB_GMCH_GMS_STOLEN_256M:

			stolen_size = MB(256);

			break;

		case SNB_GMCH_GMS_STOLEN_288M:

			stolen_size = MB(288);

			break;

		case SNB_GMCH_GMS_STOLEN_320M:

			stolen_size = MB(320);

			break;

		case SNB_GMCH_GMS_STOLEN_352M:

			stolen_size = MB(352);

			break;

		case SNB_GMCH_GMS_STOLEN_384M:

			stolen_size = MB(384);

			break;

		case SNB_GMCH_GMS_STOLEN_416M:

			stolen_size = MB(416);

			break;

		case SNB_GMCH_GMS_STOLEN_448M:

			stolen_size = MB(448);

			break;

		case SNB_GMCH_GMS_STOLEN_480M:

			stolen_size = MB(480);

			break;

		case SNB_GMCH_GMS_STOLEN_512M:

			stolen_size = MB(512);

			break;

		}

	} else {

		switch (gmch_ctrl & I855_GMCH_GMS_MASK) {

		case I855_GMCH_GMS_STOLEN_1M:
@@ -556,29 +500,9 @@ static unsigned int i965_gtt_total_entries(void) 


static unsigned int intel_gtt_total_entries(void)

{

	int size;



	if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)

		return i965_gtt_total_entries();

	else if (INTEL_GTT_GEN == 6) {

		u16 snb_gmch_ctl;



		pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);

		switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {

		default:

		case SNB_GTT_SIZE_0M:

			printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);

			size = MB(0);

			break;

		case SNB_GTT_SIZE_1M:

			size = MB(1);

			break;

		case SNB_GTT_SIZE_2M:

			size = MB(2);

			break;

		}

		return size/4;

	} else {

	else {

		/* On previous hardware, the GTT size was just what was

		 * required to map the aperture.

		 */
@@ -778,9 +702,6 @@ bool intel_enable_gtt(void) 
{

	u8 __iomem *reg;



	if (INTEL_GTT_GEN >= 6)

	    return true;



	if (INTEL_GTT_GEN == 2) {

		u16 gmch_ctrl;
@@ -1149,85 +1070,6 @@ static void i965_write_entry(dma_addr_t addr, 
	writel(addr | pte_flags, intel_private.gtt + entry);

}



static bool gen6_check_flags(unsigned int flags)

{

	return true;

}



static void haswell_write_entry(dma_addr_t addr, unsigned int entry,

				unsigned int flags)

{

	unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;

	unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;

	u32 pte_flags;



	if (type_mask == AGP_USER_MEMORY)

		pte_flags = HSW_PTE_UNCACHED | I810_PTE_VALID;

	else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {

		pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;

		if (gfdt)

			pte_flags |= GEN6_PTE_GFDT;

	} else { /* set 'normal'/'cached' to LLC by default */

		pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;

		if (gfdt)

			pte_flags |= GEN6_PTE_GFDT;

	}



	/* gen6 has bit11-4 for physical addr bit39-32 */

	addr |= (addr >> 28) & 0xff0;

	writel(addr | pte_flags, intel_private.gtt + entry);

}



static void gen6_write_entry(dma_addr_t addr, unsigned int entry,

			     unsigned int flags)

{

	unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;

	unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;

	u32 pte_flags;



	if (type_mask == AGP_USER_MEMORY)

		pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;

	else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {

		pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;

		if (gfdt)

			pte_flags |= GEN6_PTE_GFDT;

	} else { /* set 'normal'/'cached' to LLC by default */

		pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;

		if (gfdt)

			pte_flags |= GEN6_PTE_GFDT;

	}



	/* gen6 has bit11-4 for physical addr bit39-32 */

	addr |= (addr >> 28) & 0xff0;

	writel(addr | pte_flags, intel_private.gtt + entry);

}



static void valleyview_write_entry(dma_addr_t addr, unsigned int entry,

				   unsigned int flags)

{

	unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;

	unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;

	u32 pte_flags;



	if (type_mask == AGP_USER_MEMORY)

		pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;

	else {

		pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;

		if (gfdt)

			pte_flags |= GEN6_PTE_GFDT;

	}



	/* gen6 has bit11-4 for physical addr bit39-32 */

	addr |= (addr >> 28) & 0xff0;

	writel(addr | pte_flags, intel_private.gtt + entry);



	writel(1, intel_private.registers + GFX_FLSH_CNTL_VLV);

}



static void gen6_cleanup(void)

{

}



/* Certain Gen5 chipsets require require idling the GPU before

 * unmapping anything from the GTT when VT-d is enabled.

 */
@@ -1249,42 +1091,30 @@ static inline int needs_idle_maps(void) 


static int i9xx_setup(void)

{

	u32 reg_addr;

	u32 reg_addr, gtt_addr;

	int size = KB(512);



	pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);



	reg_addr &= 0xfff80000;



	if (INTEL_GTT_GEN >= 7)

		size = MB(2);



	intel_private.registers = ioremap(reg_addr, size);

	if (!intel_private.registers)

		return -ENOMEM;



	if (INTEL_GTT_GEN == 3) {

		u32 gtt_addr;



	switch (INTEL_GTT_GEN) {

	case 3:

		pci_read_config_dword(intel_private.pcidev,

				      I915_PTEADDR, &gtt_addr);

		intel_private.gtt_bus_addr = gtt_addr;

	} else {

		u32 gtt_offset;



		switch (INTEL_GTT_GEN) {

		break;

	case 5:

		case 6:

		case 7:

			gtt_offset = MB(2);

		intel_private.gtt_bus_addr = reg_addr + MB(2);

		break;

		case 4:

	default:

			gtt_offset =  KB(512);

		intel_private.gtt_bus_addr = reg_addr + KB(512);

		break;

	}

		intel_private.gtt_bus_addr = reg_addr + gtt_offset;

	}



	if (needs_idle_maps())

		intel_private.base.do_idle_maps = 1;
@@ -1395,32 +1225,6 @@ static const struct intel_gtt_driver ironlake_gtt_driver = { 
	.check_flags = i830_check_flags,

	.chipset_flush = i9xx_chipset_flush,

};

static const struct intel_gtt_driver sandybridge_gtt_driver = {

	.gen = 6,

	.setup = i9xx_setup,

	.cleanup = gen6_cleanup,

	.write_entry = gen6_write_entry,

	.dma_mask_size = 40,

	.check_flags = gen6_check_flags,

	.chipset_flush = i9xx_chipset_flush,

};

static const struct intel_gtt_driver haswell_gtt_driver = {

	.gen = 6,

	.setup = i9xx_setup,

	.cleanup = gen6_cleanup,

	.write_entry = haswell_write_entry,

	.dma_mask_size = 40,

	.check_flags = gen6_check_flags,

	.chipset_flush = i9xx_chipset_flush,

};

static const struct intel_gtt_driver valleyview_gtt_driver = {

	.gen = 7,

	.setup = i9xx_setup,

	.cleanup = gen6_cleanup,

	.write_entry = valleyview_write_entry,

	.dma_mask_size = 40,

	.check_flags = gen6_check_flags,

};



/* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of

 * driver and gmch_driver must be non-null, and find_gmch will determine
@@ -1501,106 +1305,6 @@ static const struct intel_gtt_driver_description { 
	    "HD Graphics", &ironlake_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,

	    "HD Graphics", &ironlake_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,

	    "Sandybridge", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,

	    "Sandybridge", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,

	    "Sandybridge", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,

	    "Sandybridge", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,

	    "Sandybridge", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,

	    "Sandybridge", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,

	    "Sandybridge", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG,

	    "Ivybridge", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG,

	    "Ivybridge", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG,

	    "Ivybridge", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG,

	    "Ivybridge", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,

	    "Ivybridge", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG,

	    "Ivybridge", &sandybridge_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG,

	    "ValleyView", &valleyview_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG,

	    "Haswell", &haswell_gtt_driver },

	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG,

	    "Haswell", &haswell_gtt_driver },

	{ 0, NULL, NULL }

};
@@ -1686,7 +1390,7 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, 
}

EXPORT_SYMBOL(intel_gmch_probe);



const struct intel_gtt *intel_gtt_get(void)

struct intel_gtt *intel_gtt_get(void)

{

	return &intel_private.base;

}

drivers/gpu/drm/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ drm-$(CONFIG_DRM_GEM_CMA_HELPER) += drm_gem_cma_helper.o 


drm-usb-y   := drm_usb.o



drm_kms_helper-y := drm_fb_helper.o drm_crtc_helper.o drm_dp_i2c_helper.o

drm_kms_helper-y := drm_fb_helper.o drm_crtc_helper.o drm_dp_helper.o

drm_kms_helper-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o

drm_kms_helper-$(CONFIG_DRM_KMS_CMA_HELPER) += drm_fb_cma_helper.o

drivers/gpu/drm/drm_crtc_helper.c

+18 −0
Original line number Diff line number Diff line
@@ -39,6 +39,24 @@ 
#include <drm/drm_fb_helper.h>

#include <drm/drm_edid.h>



void drm_helper_move_panel_connectors_to_head(struct drm_device *dev)

{

	struct drm_connector *connector, *tmp;

	struct list_head panel_list;



	INIT_LIST_HEAD(&panel_list);



	list_for_each_entry_safe(connector, tmp,

				 &dev->mode_config.connector_list, head) {

		if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS ||

		    connector->connector_type == DRM_MODE_CONNECTOR_eDP)

			list_move_tail(&connector->head, &panel_list);

	}



	list_splice(&panel_list, &dev->mode_config.connector_list);

}

EXPORT_SYMBOL(drm_helper_move_panel_connectors_to_head);



static bool drm_kms_helper_poll = true;

module_param_named(poll, drm_kms_helper_poll, bool, 0600);

drivers/gpu/drm/drm_dp_i2c_helper.c→drivers/gpu/drm/drm_dp_helper.c

+122 −3
Original line number Diff line number Diff line
@@ -182,7 +182,6 @@ i2c_dp_aux_reset_bus(struct i2c_adapter *adapter) 
{

	(void) i2c_algo_dp_aux_address(adapter, 0, false);

	(void) i2c_algo_dp_aux_stop(adapter, false);

					   

}



static int
@@ -206,3 +205,123 @@ i2c_dp_aux_add_bus(struct i2c_adapter *adapter) 
	return error;

}

EXPORT_SYMBOL(i2c_dp_aux_add_bus);



/* Helpers for DP link training */

static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)

{

	return link_status[r - DP_LANE0_1_STATUS];

}



static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],

			     int lane)

{

	int i = DP_LANE0_1_STATUS + (lane >> 1);

	int s = (lane & 1) * 4;

	u8 l = dp_link_status(link_status, i);

	return (l >> s) & 0xf;

}



bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],

			  int lane_count)

{

	u8 lane_align;

	u8 lane_status;

	int lane;



	lane_align = dp_link_status(link_status,

				    DP_LANE_ALIGN_STATUS_UPDATED);

	if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)

		return false;

	for (lane = 0; lane < lane_count; lane++) {

		lane_status = dp_get_lane_status(link_status, lane);

		if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)

			return false;

	}

	return true;

}

EXPORT_SYMBOL(drm_dp_channel_eq_ok);



bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],

			      int lane_count)

{

	int lane;

	u8 lane_status;



	for (lane = 0; lane < lane_count; lane++) {

		lane_status = dp_get_lane_status(link_status, lane);

		if ((lane_status & DP_LANE_CR_DONE) == 0)

			return false;

	}

	return true;

}

EXPORT_SYMBOL(drm_dp_clock_recovery_ok);



u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],

				     int lane)

{

	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);

	int s = ((lane & 1) ?

		 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :

		 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);

	u8 l = dp_link_status(link_status, i);



	return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;

}

EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);



u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],

					  int lane)

{

	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);

	int s = ((lane & 1) ?

		 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :

		 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);

	u8 l = dp_link_status(link_status, i);



	return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;

}

EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);



void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {

	if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)

		udelay(100);

	else

		mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);

}

EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);



void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {

	if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)

		udelay(400);

	else

		mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);

}

EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);



u8 drm_dp_link_rate_to_bw_code(int link_rate)

{

	switch (link_rate) {

	case 162000:

	default:

		return DP_LINK_BW_1_62;

	case 270000:

		return DP_LINK_BW_2_7;

	case 540000:

		return DP_LINK_BW_5_4;

	}

}

EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);



int drm_dp_bw_code_to_link_rate(u8 link_bw)

{

	switch (link_bw) {

	case DP_LINK_BW_1_62:

	default:

		return 162000;

	case DP_LINK_BW_2_7:

		return 270000;

	case DP_LINK_BW_5_4:

		return 540000;

	}

}

EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);