Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9f9a35a7 authored by Tomasz Nowicki's avatar Tomasz Nowicki Committed by Rafael J. Wysocki
Browse files

ACPI / APEI / ARM64: APEI initial support for ARM64 



This patch provides APEI arch-specific bits for ARM64

Meanwhile,
 (1) Move HEST type (ACPI_HEST_TYPE_IA32_CORRECTED_CHECK) checking to
     a generic place.
 (2) Select HAVE_ACPI_APEI when EFI and ACPI is set on ARM64, because
     arch_apei_get_mem_attribute is using efi_mem_attributes() on
     ARM64.

Signed-off-by: default avatarTomasz Nowicki <tomasz.nowicki@linaro.org>
Tested-by: default avatarJonathan (Zhixiong) Zhang <zjzhang@codeaurora.org>
Signed-off-by: default avatarFu Wei <fu.wei@linaro.org>
[ Fu Wei: improve && upstream ]
Acked-by: default avatarHanjun Guo <hanjun.guo@linaro.org>
Tested-by: default avatarTyler Baicar <tbaicar@codeaurora.org>
Acked-by: default avatarWill Deacon <will.deacon@arm.com>
Reviewed-by: default avatarBorislav Petkov <bp@suse.de>
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent a545715d

arch/arm64/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ config ARM64 
	select GENERIC_TIME_VSYSCALL

	select HANDLE_DOMAIN_IRQ

	select HARDIRQS_SW_RESEND

	select HAVE_ACPI_APEI if (ACPI && EFI)

	select HAVE_ALIGNED_STRUCT_PAGE if SLUB

	select HAVE_ARCH_AUDITSYSCALL

	select HAVE_ARCH_BITREVERSE

arch/arm64/include/asm/acpi.h

+22 −1
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 


#include <asm/cputype.h>

#include <asm/smp_plat.h>

#include <asm/tlbflush.h>



/* Macros for consistency checks of the GICC subtable of MADT */

#define ACPI_MADT_GICC_LENGTH	\
@@ -114,8 +115,28 @@ static inline const char *acpi_get_enable_method(int cpu) 
}



#ifdef	CONFIG_ACPI_APEI

/*

 * acpi_disable_cmcff is used in drivers/acpi/apei/hest.c for disabling

 * IA-32 Architecture Corrected Machine Check (CMC) Firmware-First mode

 * with a kernel command line parameter "acpi=nocmcoff". But we don't

 * have this IA-32 specific feature on ARM64, this definition is only

 * for compatibility.

 */

#define acpi_disable_cmcff 1

pgprot_t arch_apei_get_mem_attribute(phys_addr_t addr);

#endif



/*

 * Despite its name, this function must still broadcast the TLB

 * invalidation in order to ensure other CPUs don't end up with junk

 * entries as a result of speculation. Unusually, its also called in

 * IRQ context (ghes_iounmap_irq) so if we ever need to use IPIs for

 * TLB broadcasting, then we're in trouble here.

 */

static inline void arch_apei_flush_tlb_one(unsigned long addr)

{

	flush_tlb_kernel_range(addr, addr + PAGE_SIZE);

}

#endif /* CONFIG_ACPI_APEI */



#ifdef CONFIG_ACPI_NUMA

int arm64_acpi_numa_init(void);

arch/x86/kernel/acpi/apei.c

+0 −3
Original line number Diff line number Diff line
@@ -24,9 +24,6 @@ int arch_apei_enable_cmcff(struct acpi_hest_header *hest_hdr, void *data) 
	struct acpi_hest_ia_corrected *cmc;

	struct acpi_hest_ia_error_bank *mc_bank;



	if (hest_hdr->type != ACPI_HEST_TYPE_IA32_CORRECTED_CHECK)

		return 0;



	cmc = (struct acpi_hest_ia_corrected *)hest_hdr;

	if (!cmc->enabled)

		return 0;

drivers/acpi/apei/hest.c

+10 −3
Original line number Diff line number Diff line
@@ -123,7 +123,13 @@ EXPORT_SYMBOL_GPL(apei_hest_parse); 
 */

static int __init hest_parse_cmc(struct acpi_hest_header *hest_hdr, void *data)

{

	return arch_apei_enable_cmcff(hest_hdr, data);

	if (hest_hdr->type != ACPI_HEST_TYPE_IA32_CORRECTED_CHECK)

		return 0;



	if (!acpi_disable_cmcff)

		return !arch_apei_enable_cmcff(hest_hdr, data);



	return 0;

}



struct ghes_arr {
@@ -232,8 +238,9 @@ void __init acpi_hest_init(void) 
		goto err;

	}



	if (!acpi_disable_cmcff)

		apei_hest_parse(hest_parse_cmc, NULL);

	rc = apei_hest_parse(hest_parse_cmc, NULL);

	if (rc)

		goto err;



	if (!ghes_disable) {

		rc = apei_hest_parse(hest_parse_ghes_count, &ghes_count);