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Commit 9f65fb29 authored by Konrad Rzeszutek Wilk's avatar Konrad Rzeszutek Wilk Committed by Thomas Gleixner
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x86/bugs: Rename _RDS to _SSBD 



Intel collateral will reference the SSB mitigation bit in IA32_SPEC_CTL[2]
as SSBD (Speculative Store Bypass Disable).

Hence changing it.

It is unclear yet what the MSR_IA32_ARCH_CAPABILITIES (0x10a) Bit(4) name
is going to be. Following the rename it would be SSBD_NO but that rolls out
to Speculative Store Bypass Disable No.

Also fixed the missing space in X86_FEATURE_AMD_SSBD.

[ tglx: Fixup x86_amd_rds_enable() and rds_tif_to_amd_ls_cfg() as well ]

Signed-off-by: default avatarKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent f21b53b2

arch/x86/include/asm/cpufeatures.h

+2 −2
Original line number Diff line number Diff line
@@ -215,7 +215,7 @@ 
#define X86_FEATURE_USE_IBPB		( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */

#define X86_FEATURE_USE_IBRS_FW		( 7*32+22) /* "" Use IBRS during runtime firmware calls */

#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE	( 7*32+23) /* "" Disable Speculative Store Bypass. */

#define X86_FEATURE_AMD_RDS		(7*32+24)  /* "" AMD RDS implementation */

#define X86_FEATURE_AMD_SSBD		( 7*32+24)  /* "" AMD SSBD implementation */



/* Virtualization flags: Linux defined, word 8 */

#define X86_FEATURE_TPR_SHADOW		( 8*32+ 0) /* Intel TPR Shadow */
@@ -336,7 +336,7 @@ 
#define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */

#define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */

#define X86_FEATURE_ARCH_CAPABILITIES	(18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */

#define X86_FEATURE_RDS			(18*32+31) /* Reduced Data Speculation */

#define X86_FEATURE_SSBD		(18*32+31) /* Speculative Store Bypass Disable */



/*

 * BUG word(s)

arch/x86/include/asm/msr-index.h

+5 −5
Original line number Diff line number Diff line
@@ -42,8 +42,8 @@ 
#define MSR_IA32_SPEC_CTRL		0x00000048 /* Speculation Control */

#define SPEC_CTRL_IBRS			(1 << 0)   /* Indirect Branch Restricted Speculation */

#define SPEC_CTRL_STIBP			(1 << 1)   /* Single Thread Indirect Branch Predictors */

#define SPEC_CTRL_RDS_SHIFT		2	   /* Reduced Data Speculation bit */

#define SPEC_CTRL_RDS			(1 << SPEC_CTRL_RDS_SHIFT)   /* Reduced Data Speculation */

#define SPEC_CTRL_SSBD_SHIFT		2	   /* Speculative Store Bypass Disable bit */

#define SPEC_CTRL_SSBD			(1 << SPEC_CTRL_SSBD_SHIFT)   /* Speculative Store Bypass Disable */



#define MSR_IA32_PRED_CMD		0x00000049 /* Prediction Command */

#define PRED_CMD_IBPB			(1 << 0)   /* Indirect Branch Prediction Barrier */
@@ -70,10 +70,10 @@ 
#define MSR_IA32_ARCH_CAPABILITIES	0x0000010a

#define ARCH_CAP_RDCL_NO		(1 << 0)   /* Not susceptible to Meltdown */

#define ARCH_CAP_IBRS_ALL		(1 << 1)   /* Enhanced IBRS support */

#define ARCH_CAP_RDS_NO			(1 << 4)   /*

#define ARCH_CAP_SSBD_NO		(1 << 4)   /*

						    * Not susceptible to Speculative Store Bypass

						    * attack, so no Reduced Data Speculation control

						    * required.

						    * attack, so no Speculative Store Bypass

						    * control required.

						    */



#define MSR_IA32_BBL_CR_CTL		0x00000119

arch/x86/include/asm/spec-ctrl.h

+6 −6
Original line number Diff line number Diff line
@@ -17,20 +17,20 @@ extern void x86_spec_ctrl_restore_host(u64); 


/* AMD specific Speculative Store Bypass MSR data */

extern u64 x86_amd_ls_cfg_base;

extern u64 x86_amd_ls_cfg_rds_mask;

extern u64 x86_amd_ls_cfg_ssbd_mask;



/* The Intel SPEC CTRL MSR base value cache */

extern u64 x86_spec_ctrl_base;



static inline u64 rds_tif_to_spec_ctrl(u64 tifn)

static inline u64 ssbd_tif_to_spec_ctrl(u64 tifn)

{

	BUILD_BUG_ON(TIF_RDS < SPEC_CTRL_RDS_SHIFT);

	return (tifn & _TIF_RDS) >> (TIF_RDS - SPEC_CTRL_RDS_SHIFT);

	BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT);

	return (tifn & _TIF_SSBD) >> (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT);

}



static inline u64 rds_tif_to_amd_ls_cfg(u64 tifn)

static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn)

{

	return (tifn & _TIF_RDS) ? x86_amd_ls_cfg_rds_mask : 0ULL;

	return (tifn & _TIF_SSBD) ? x86_amd_ls_cfg_ssbd_mask : 0ULL;

}



extern void speculative_store_bypass_update(void);

arch/x86/include/asm/thread_info.h

+3 −3
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@ struct thread_info { 
#define TIF_SIGPENDING		2	/* signal pending */

#define TIF_NEED_RESCHED	3	/* rescheduling necessary */

#define TIF_SINGLESTEP		4	/* reenable singlestep on user return*/

#define TIF_RDS			5	/* Reduced data speculation */

#define TIF_SSBD			5	/* Reduced data speculation */

#define TIF_SYSCALL_EMU		6	/* syscall emulation active */

#define TIF_SYSCALL_AUDIT	7	/* syscall auditing active */

#define TIF_SECCOMP		8	/* secure computing */
@@ -106,7 +106,7 @@ struct thread_info { 
#define _TIF_SIGPENDING		(1 << TIF_SIGPENDING)

#define _TIF_NEED_RESCHED	(1 << TIF_NEED_RESCHED)

#define _TIF_SINGLESTEP		(1 << TIF_SINGLESTEP)

#define _TIF_RDS		(1 << TIF_RDS)

#define _TIF_SSBD		(1 << TIF_SSBD)

#define _TIF_SYSCALL_EMU	(1 << TIF_SYSCALL_EMU)

#define _TIF_SYSCALL_AUDIT	(1 << TIF_SYSCALL_AUDIT)

#define _TIF_SECCOMP		(1 << TIF_SECCOMP)
@@ -146,7 +146,7 @@ struct thread_info { 


/* flags to check in __switch_to() */

#define _TIF_WORK_CTXSW							\

	(_TIF_IO_BITMAP|_TIF_NOCPUID|_TIF_NOTSC|_TIF_BLOCKSTEP|_TIF_RDS)

	(_TIF_IO_BITMAP|_TIF_NOCPUID|_TIF_NOTSC|_TIF_BLOCKSTEP|_TIF_SSBD)



#define _TIF_WORK_CTXSW_PREV (_TIF_WORK_CTXSW|_TIF_USER_RETURN_NOTIFY)

#define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW)

arch/x86/kernel/cpu/amd.c

+7 −7
Original line number Diff line number Diff line
@@ -567,12 +567,12 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) 
		}

		/*

		 * Try to cache the base value so further operations can

		 * avoid RMW. If that faults, do not enable RDS.

		 * avoid RMW. If that faults, do not enable SSBD.

		 */

		if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {

			setup_force_cpu_cap(X86_FEATURE_RDS);

			setup_force_cpu_cap(X86_FEATURE_AMD_RDS);

			x86_amd_ls_cfg_rds_mask = 1ULL << bit;

			setup_force_cpu_cap(X86_FEATURE_SSBD);

			setup_force_cpu_cap(X86_FEATURE_AMD_SSBD);

			x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;

		}

	}

}
@@ -920,9 +920,9 @@ static void init_amd(struct cpuinfo_x86 *c) 
	if (!cpu_has(c, X86_FEATURE_XENPV))

		set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);



	if (boot_cpu_has(X86_FEATURE_AMD_RDS)) {

		set_cpu_cap(c, X86_FEATURE_RDS);

		set_cpu_cap(c, X86_FEATURE_AMD_RDS);

	if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) {

		set_cpu_cap(c, X86_FEATURE_SSBD);

		set_cpu_cap(c, X86_FEATURE_AMD_SSBD);

	}

}