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Commit 9f436c46 authored by Michal Wajdeczko's avatar Michal Wajdeczko Committed by Joonas Lahtinen
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drm/i915/guc: Move GuC submission declarations into dedicated header 



Move GuC submission declarations into dedicated header as we want to
keep uC specific code in separate files.

v2: fix include (Chris)
    update commit message (Joonas)

Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: MichaĹ Winiarski <michal.winiarski@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171004181343.66348-3-michal.wajdeczko@intel.com
parent d62e2bf3

drivers/gpu/drm/i915/i915_debugfs.c

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 
#include <linux/sort.h>

#include <linux/sched/mm.h>

#include "intel_drv.h"

#include "i915_guc_submission.h"



static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)

{

drivers/gpu/drm/i915/i915_guc_submission.c

+4 −3
Original line number Diff line number Diff line
@@ -21,12 +21,13 @@ 
 * IN THE SOFTWARE.

 *

 */

#include <linux/circ_buf.h>

#include "i915_drv.h"

#include "intel_uc.h"



#include <linux/circ_buf.h>

#include <trace/events/dma_fence.h>



#include "i915_guc_submission.h"

#include "i915_drv.h"



/**

 * DOC: GuC-based command submission

 *

drivers/gpu/drm/i915/i915_guc_submission.h

0 → 100644
+80 −0
Original line number Diff line number Diff line 
/*

 * Copyright © 2014-2017 Intel Corporation

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice (including the next

 * paragraph) shall be included in all copies or substantial portions of the

 * Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS

 * IN THE SOFTWARE.

 *

 */



#ifndef _I915_GUC_SUBMISSION_H_

#define _I915_GUC_SUBMISSION_H_



#include <linux/spinlock.h>



#include "i915_gem.h"



struct drm_i915_private;



/*

 * This structure primarily describes the GEM object shared with the GuC.

 * The specs sometimes refer to this object as a "GuC context", but we use

 * the term "client" to avoid confusion with hardware contexts. This

 * GEM object is held for the entire lifetime of our interaction with

 * the GuC, being allocated before the GuC is loaded with its firmware.

 * Because there's no way to update the address used by the GuC after

 * initialisation, the shared object must stay pinned into the GGTT as

 * long as the GuC is in use. We also keep the first page (only) mapped

 * into kernel address space, as it includes shared data that must be

 * updated on every request submission.

 *

 * The single GEM object described here is actually made up of several

 * separate areas, as far as the GuC is concerned. The first page (kept

 * kmap'd) includes the "process descriptor" which holds sequence data for

 * the doorbell, and one cacheline which actually *is* the doorbell; a

 * write to this will "ring the doorbell" (i.e. send an interrupt to the

 * GuC). The subsequent  pages of the client object constitute the work

 * queue (a circular array of work items), again described in the process

 * descriptor. Work queue pages are mapped momentarily as required.

 */

struct i915_guc_client {

	struct i915_vma *vma;

	void *vaddr;

	struct i915_gem_context *owner;

	struct intel_guc *guc;



	/* bitmap of (host) engine ids */

	uint32_t engines;

	uint32_t priority;

	u32 stage_id;

	uint32_t proc_desc_offset;



	u16 doorbell_id;

	unsigned long doorbell_offset;



	spinlock_t wq_lock;

	/* Per-engine counts of GuC submissions */

	uint64_t submissions[I915_NUM_ENGINES];

};



int i915_guc_submission_init(struct drm_i915_private *dev_priv);

int i915_guc_submission_enable(struct drm_i915_private *dev_priv);

void i915_guc_submission_disable(struct drm_i915_private *dev_priv);

void i915_guc_submission_fini(struct drm_i915_private *dev_priv);



#endif

drivers/gpu/drm/i915/intel_uc.c

+1 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 


#include "i915_drv.h"

#include "intel_uc.h"

#include "i915_guc_submission.h"

#include <linux/firmware.h>



/* Reset GuC providing us with fresh state for both GuC and HuC.

drivers/gpu/drm/i915/intel_uc.h

+0 −45
Original line number Diff line number Diff line
@@ -33,46 +33,6 @@ 
#include "i915_vma.h"

#include "intel_huc.h"



/*

 * This structure primarily describes the GEM object shared with the GuC.

 * The specs sometimes refer to this object as a "GuC context", but we use

 * the term "client" to avoid confusion with hardware contexts. This

 * GEM object is held for the entire lifetime of our interaction with

 * the GuC, being allocated before the GuC is loaded with its firmware.

 * Because there's no way to update the address used by the GuC after

 * initialisation, the shared object must stay pinned into the GGTT as

 * long as the GuC is in use. We also keep the first page (only) mapped

 * into kernel address space, as it includes shared data that must be

 * updated on every request submission.

 *

 * The single GEM object described here is actually made up of several

 * separate areas, as far as the GuC is concerned. The first page (kept

 * kmap'd) includes the "process descriptor" which holds sequence data for

 * the doorbell, and one cacheline which actually *is* the doorbell; a

 * write to this will "ring the doorbell" (i.e. send an interrupt to the

 * GuC). The subsequent  pages of the client object constitute the work

 * queue (a circular array of work items), again described in the process

 * descriptor. Work queue pages are mapped momentarily as required.

 */

struct i915_guc_client {

	struct i915_vma *vma;

	void *vaddr;

	struct i915_gem_context *owner;

	struct intel_guc *guc;



	uint32_t engines;		/* bitmap of (host) engine ids	*/

	uint32_t priority;

	u32 stage_id;

	uint32_t proc_desc_offset;



	u16 doorbell_id;

	unsigned long doorbell_offset;



	spinlock_t wq_lock;

	/* Per-engine counts of GuC submissions */

	uint64_t submissions[I915_NUM_ENGINES];

};



struct intel_guc {

	struct intel_uc_fw fw;

	struct intel_guc_log log;
@@ -141,11 +101,6 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv); 
int intel_guc_resume(struct drm_i915_private *dev_priv);

u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);



/* i915_guc_submission.c */

int i915_guc_submission_init(struct drm_i915_private *dev_priv);

int i915_guc_submission_enable(struct drm_i915_private *dev_priv);

void i915_guc_submission_disable(struct drm_i915_private *dev_priv);

void i915_guc_submission_fini(struct drm_i915_private *dev_priv);

struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);



static inline u32 guc_ggtt_offset(struct i915_vma *vma)