Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9e43eca3 authored by Marek Szyprowski's avatar Marek Szyprowski Committed by Krzysztof Kozlowski
Browse files

ARM: EXYNOS: Remove Exynos4212 related dead code 



Support for Exynos4212 SoCs has been removed by commit bca9085e ("ARM:
dts: exynos: remove Exynos4212 support (dead code)"), so there is no need
to keep remaining dead code related to this SoC version.

Signed-off-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parent 09e1cf82

arch/arm/mach-exynos/Kconfig

+0 −5
Original line number Diff line number Diff line
@@ -85,11 +85,6 @@ config CPU_EXYNOS4210 
	default y

	depends on ARCH_EXYNOS4



config SOC_EXYNOS4212

	bool "SAMSUNG EXYNOS4212"

	default y

	depends on ARCH_EXYNOS4



config SOC_EXYNOS4412

	bool "SAMSUNG EXYNOS4412"

	default y

arch/arm/mach-exynos/common.h

+1 −10
Original line number Diff line number Diff line
@@ -18,7 +18,6 @@ 
#define EXYNOS3_SOC_MASK	0xFFFFF000



#define EXYNOS4210_CPU_ID	0x43210000

#define EXYNOS4212_CPU_ID	0x43220000

#define EXYNOS4412_CPU_ID	0xE4412200

#define EXYNOS4_CPU_MASK	0xFFFE0000
@@ -39,7 +38,6 @@ static inline int is_samsung_##name(void) \ 


IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK)

IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)

IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)

IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)

IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)

IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
@@ -59,12 +57,6 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) 
# define soc_is_exynos4210()	0

#endif



#if defined(CONFIG_SOC_EXYNOS4212)

# define soc_is_exynos4212()	is_samsung_exynos4212()

#else

# define soc_is_exynos4212()	0

#endif



#if defined(CONFIG_SOC_EXYNOS4412)

# define soc_is_exynos4412()	is_samsung_exynos4412()

#else
@@ -105,8 +97,7 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) 
# define soc_is_exynos5800()	0

#endif



#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \

			  soc_is_exynos4412())

#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4412())

#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \

			  soc_is_exynos5420() || soc_is_exynos5800())

arch/arm/mach-exynos/exynos.c

+0 −2
Original line number Diff line number Diff line
@@ -195,7 +195,6 @@ static void __init exynos_dt_machine_init(void) 
		exynos_cpuidle.dev.platform_data = &cpuidle_coupled_exynos_data;

#endif

	if (of_machine_is_compatible("samsung,exynos4210") ||

	    of_machine_is_compatible("samsung,exynos4212") ||

	    (of_machine_is_compatible("samsung,exynos4412") &&

	     of_machine_is_compatible("samsung,trats2")) ||

	    of_machine_is_compatible("samsung,exynos3250") ||
@@ -208,7 +207,6 @@ static char const *const exynos_dt_compat[] __initconst = { 
	"samsung,exynos3250",

	"samsung,exynos4",

	"samsung,exynos4210",

	"samsung,exynos4212",

	"samsung,exynos4412",

	"samsung,exynos5",

	"samsung,exynos5250",

arch/arm/mach-exynos/firmware.c

+0 −5
Original line number Diff line number Diff line
@@ -70,12 +70,7 @@ static int exynos_cpu_boot(int cpu) 


	/*

	 * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.

	 * But, Exynos4212 has only one secondary CPU so second parameter

	 * isn't used for informing secure firmware about CPU id.

	 */

	if (soc_is_exynos4212())

		cpu = 0;



	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);

	return 0;

}

arch/arm/mach-exynos/pm.c

+1 −2
Original line number Diff line number Diff line
@@ -167,8 +167,7 @@ void exynos_enter_aftr(void) 


	exynos_pm_central_suspend();



	if (of_machine_is_compatible("samsung,exynos4212") ||

	    of_machine_is_compatible("samsung,exynos4412")) {

	if (of_machine_is_compatible("samsung,exynos4412")) {

		/* Setting SEQ_OPTION register */

		pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,

			       S5P_CENTRAL_SEQ_OPTION);