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Commit 9e1d0e60 authored by Michel Thierry's avatar Michel Thierry Committed by Tvrtko Ursulin
Browse files

drm/i915: Advertise ppgtt support type in platform definition 



Instead of being hidden in sanitize_enable_ppgtt.
It also seems to be the place to do so nowadays.

Signed-off-by: default avatarMichel Thierry <michel.thierry@intel.com>
Reviewed-by: default avatarMichał Winiarski <michal.winiarski@intel.com>
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
parent d637c178

drivers/gpu/drm/i915/i915_drv.h

+3 −0
Original line number Diff line number Diff line
@@ -710,11 +710,14 @@ struct intel_csr { 
	func(is_alpha_support); \

	/* Keep has_* in alphabetical order */ \

	func(has_64bit_reloc); \

	func(has_aliasing_ppgtt); \

	func(has_csr); \

	func(has_ddi); \

	func(has_dp_mst); \

	func(has_fbc); \

	func(has_fpga_dbg); \

	func(has_full_ppgtt); \

	func(has_full_48bit_ppgtt); \

	func(has_gmbus_irq); \

	func(has_gmch_display); \

	func(has_guc); \

drivers/gpu/drm/i915/i915_gem_gtt.c

+3 −4
Original line number Diff line number Diff line
@@ -113,10 +113,9 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, 
	bool has_full_ppgtt;

	bool has_full_48bit_ppgtt;



	has_aliasing_ppgtt = INTEL_GEN(dev_priv) >= 6;

	has_full_ppgtt = INTEL_GEN(dev_priv) >= 7;

	has_full_48bit_ppgtt =

	       	IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9;

	has_aliasing_ppgtt = dev_priv->info.has_aliasing_ppgtt;

	has_full_ppgtt = dev_priv->info.has_full_ppgtt;

	has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;



	if (intel_vgpu_active(dev_priv)) {

		/* emulation is too hard */

drivers/gpu/drm/i915/i915_pci.c

+11 −0
Original line number Diff line number Diff line
@@ -204,6 +204,7 @@ static const struct intel_device_info intel_ironlake_m_info = { 
	.has_rc6p = 1, \

	.has_gmbus_irq = 1, \

	.has_hw_contexts = 1, \

	.has_aliasing_ppgtt = 1, \

	GEN_DEFAULT_PIPEOFFSETS, \

	CURSOR_OFFSETS
@@ -226,6 +227,8 @@ static const struct intel_device_info intel_sandybridge_m_info = { 
	.has_rc6p = 1, \

	.has_gmbus_irq = 1, \

	.has_hw_contexts = 1, \

	.has_aliasing_ppgtt = 1, \

	.has_full_ppgtt = 1, \

	GEN_DEFAULT_PIPEOFFSETS, \

	IVB_CURSOR_OFFSETS
@@ -258,6 +261,8 @@ static const struct intel_device_info intel_ivybridge_q_info = { 
	.has_hw_contexts = 1, \

	.has_gmch_display = 1, \

	.has_hotplug = 1, \

	.has_aliasing_ppgtt = 1, \

	.has_full_ppgtt = 1, \

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \

	.display_mmio_offset = VLV_DISPLAY_BASE, \

	GEN_DEFAULT_PIPEOFFSETS, \
@@ -289,6 +294,7 @@ static const struct intel_device_info intel_haswell_info = { 
	HSW_FEATURES, \

	BDW_COLORS, \

	.has_logical_ring_contexts = 1, \

	.has_full_48bit_ppgtt = 1, \

	.has_64bit_reloc = 1



static const struct intel_device_info intel_broadwell_info = {
@@ -318,6 +324,8 @@ static const struct intel_device_info intel_cherryview_info = { 
	.has_hw_contexts = 1,

	.has_logical_ring_contexts = 1,

	.has_gmch_display = 1,

	.has_aliasing_ppgtt = 1,

	.has_full_ppgtt = 1,

	.display_mmio_offset = VLV_DISPLAY_BASE,

	GEN_CHV_PIPEOFFSETS,

	CURSOR_OFFSETS,
@@ -364,6 +372,9 @@ static const struct intel_device_info intel_skylake_gt3_info = { 
	.has_logical_ring_contexts = 1, \

	.has_guc = 1, \

	.has_decoupled_mmio = 1, \

	.has_aliasing_ppgtt = 1, \

	.has_full_ppgtt = 1, \

	.has_full_48bit_ppgtt = 1, \

	GEN_DEFAULT_PIPEOFFSETS, \

	IVB_CURSOR_OFFSETS, \

	BDW_COLORS