Merge branch 'dpaa_eth-rss' (9d8c7e5a) · Commits · e / devices / android_kernel_oneplus_sm7250

Documentation/networking/dpaa.txt

+67 −1

Original line number	Diff line number	Diff line
		@@ -13,6 +13,7 @@ Contents
		- Configuring DPAA Ethernet in your kernel
		- DPAA Ethernet Frame Processing
		- DPAA Ethernet Features
		- DPAA IRQ Affinity and Receive Side Scaling
		- Debugging

		DPAA Ethernet Overview
		@@ -147,7 +148,10 @@ gradually.

		The driver has Rx and Tx checksum offloading for UDP and TCP. Currently the Rx
		checksum offload feature is enabled by default and cannot be controlled through
		ethtool.
		ethtool. Also, rx-flow-hash and rx-hashing was added. The addition of RSS
		provides a big performance boost for the forwarding scenarios, allowing
		different traffic flows received by one interface to be processed by different
		CPUs in parallel.

		The driver has support for multiple prioritized Tx traffic classes. Priorities
		range from 0 (lowest) to 3 (highest). These are mapped to HW workqueues with
		@@ -166,6 +170,68 @@ classes as follows:
		tc qdisc add dev <int> root handle 1: \
		mqprio num_tc 4 map 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 hw 1

		DPAA IRQ Affinity and Receive Side Scaling
		==========================================

		Traffic coming on the DPAA Rx queues or on the DPAA Tx confirmation
		queues is seen by the CPU as ingress traffic on a certain portal.
		The DPAA QMan portal interrupts are affined each to a certain CPU.
		The same portal interrupt services all the QMan portal consumers.

		By default the DPAA Ethernet driver enables RSS, making use of the
		DPAA FMan Parser and Keygen blocks to distribute traffic on 128
		hardware frame queues using a hash on IP v4/v6 source and destination
		and L4 source and destination ports, in present in the received frame.
		When RSS is disabled, all traffic received by a certain interface is
		received on the default Rx frame queue. The default DPAA Rx frame
		queues are configured to put the received traffic into a pool channel
		that allows any available CPU portal to dequeue the ingress traffic.
		The default frame queues have the HOLDACTIVE option set, ensuring that
		traffic bursts from a certain queue are serviced by the same CPU.
		This ensures a very low rate of frame reordering. A drawback of this
		is that only one CPU at a time can service the traffic received by a
		certain interface when RSS is not enabled.

		To implement RSS, the DPAA Ethernet driver allocates an extra set of
		128 Rx frame queues that are configured to dedicated channels, in a
		round-robin manner. The mapping of the frame queues to CPUs is now
		hardcoded, there is no indirection table to move traffic for a certain
		FQ (hash result) to another CPU. The ingress traffic arriving on one
		of these frame queues will arrive at the same portal and will always
		be processed by the same CPU. This ensures intra-flow order preservation
		and workload distribution for multiple traffic flows.

		RSS can be turned off for a certain interface using ethtool, i.e.

		# ethtool -N fm1-mac9 rx-flow-hash tcp4 ""

		To turn it back on, one needs to set rx-flow-hash for tcp4/6 or udp4/6:

		# ethtool -N fm1-mac9 rx-flow-hash udp4 sfdn

		There is no independent control for individual protocols, any command
		run for one of tcp4\|udp4\|ah4\|esp4\|sctp4\|tcp6\|udp6\|ah6\|esp6\|sctp6 is
		going to control the rx-flow-hashing for all protocols on that interface.

		Besides using the FMan Keygen computed hash for spreading traffic on the
		128 Rx FQs, the DPAA Ethernet driver also sets the skb hash value when
		the NETIF_F_RXHASH feature is on (active by default). This can be turned
		on or off through ethtool, i.e.:

		# ethtool -K fm1-mac9 rx-hashing off
		# ethtool -k fm1-mac9 \| grep hash
		receive-hashing: off
		# ethtool -K fm1-mac9 rx-hashing on
		Actual changes:
		receive-hashing: on
		# ethtool -k fm1-mac9 \| grep hash
		receive-hashing: on

		Please note that Rx hashing depends upon the rx-flow-hashing being on
		for that interface - turning off rx-flow-hashing will also disable the
		rx-hashing (without ethtool reporting it as off as that depends on the
		NETIF_F_RXHASH feature flag).

		Debugging
		=========

drivers/net/ethernet/freescale/dpaa/dpaa_eth.c

+66 −10

Original line number	Diff line number	Diff line
		@@ -158,7 +158,7 @@ MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms");
		#define DPAA_RX_PRIV_DATA_SIZE (u16)(DPAA_TX_PRIV_DATA_SIZE + \
		dpaa_rx_extra_headroom)

		#define DPAA_ETH_RX_QUEUES 128
		#define DPAA_ETH_PCD_RXQ_NUM 128

		#define DPAA_ENQUEUE_RETRIES 100000

		@@ -169,6 +169,7 @@ struct fm_port_fqs {
		struct dpaa_fq *tx_errq;
		struct dpaa_fq *rx_defq;
		struct dpaa_fq *rx_errq;
		struct dpaa_fq *rx_pcdq;
		};

		/* All the dpa bps in use at any moment */
		@@ -235,7 +236,7 @@ static int dpaa_netdev_init(struct net_device *net_dev,
		net_dev->max_mtu = dpaa_get_max_mtu();

		net_dev->hw_features \|= (NETIF_F_IP_CSUM \| NETIF_F_IPV6_CSUM \|
		NETIF_F_LLTX);
		NETIF_F_LLTX \| NETIF_F_RXHASH);

		net_dev->hw_features \|= NETIF_F_SG \| NETIF_F_HIGHDMA;
		/* The kernels enables GSO automatically, if we declare NETIF_F_SG.
		@@ -628,6 +629,7 @@ static inline void dpaa_assign_wq(struct dpaa_fq *fq, int idx)
		fq->wq = 5;
		break;
		case FQ_TYPE_RX_DEFAULT:
		case FQ_TYPE_RX_PCD:
		fq->wq = 6;
		break;
		case FQ_TYPE_TX:
		@@ -688,6 +690,7 @@ static int dpaa_alloc_all_fqs(struct device dev, struct list_head list,
		struct fm_port_fqs *port_fqs)
		{
		struct dpaa_fq *dpaa_fq;
		u32 fq_base, fq_base_aligned, i;

		dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_ERROR);
		if (!dpaa_fq)
		@@ -701,6 +704,26 @@ static int dpaa_alloc_all_fqs(struct device dev, struct list_head list,

		port_fqs->rx_defq = &dpaa_fq[0];

		/* the PCD FQIDs range needs to be aligned for correct operation */
		if (qman_alloc_fqid_range(&fq_base, 2 * DPAA_ETH_PCD_RXQ_NUM))
		goto fq_alloc_failed;

		fq_base_aligned = ALIGN(fq_base, DPAA_ETH_PCD_RXQ_NUM);

		for (i = fq_base; i < fq_base_aligned; i++)
		qman_release_fqid(i);

		for (i = fq_base_aligned + DPAA_ETH_PCD_RXQ_NUM;
		i < (fq_base + 2 * DPAA_ETH_PCD_RXQ_NUM); i++)
		qman_release_fqid(i);

		dpaa_fq = dpaa_fq_alloc(dev, fq_base_aligned, DPAA_ETH_PCD_RXQ_NUM,
		list, FQ_TYPE_RX_PCD);
		if (!dpaa_fq)
		goto fq_alloc_failed;

		port_fqs->rx_pcdq = &dpaa_fq[0];

		if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX_CONF_MQ))
		goto fq_alloc_failed;

		@@ -870,13 +893,14 @@ static void dpaa_fq_setup(struct dpaa_priv *priv,
		const struct dpaa_fq_cbs *fq_cbs,
		struct fman_port *tx_port)
		{
		int egress_cnt = 0, conf_cnt = 0, num_portals = 0, cpu;
		int egress_cnt = 0, conf_cnt = 0, num_portals = 0, portal_cnt = 0, cpu;
		const cpumask_t *affine_cpus = qman_affine_cpus();
		u16 portals[NR_CPUS];
		u16 channels[NR_CPUS];
		struct dpaa_fq *fq;

		for_each_cpu(cpu, affine_cpus)
		portals[num_portals++] = qman_affine_channel(cpu);
		channels[num_portals++] = qman_affine_channel(cpu);

		if (num_portals == 0)
		dev_err(priv->net_dev->dev.parent,
		"No Qman software (affine) channels found");
		@@ -890,6 +914,12 @@ static void dpaa_fq_setup(struct dpaa_priv *priv,
		case FQ_TYPE_RX_ERROR:
		dpaa_setup_ingress(priv, fq, &fq_cbs->rx_errq);
		break;
		case FQ_TYPE_RX_PCD:
		if (!num_portals)
		continue;
		dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq);
		fq->channel = channels[portal_cnt++ % num_portals];
		break;
		case FQ_TYPE_TX:
		dpaa_setup_egress(priv, fq, tx_port,
		&fq_cbs->egress_ern);
		@@ -1039,7 +1069,8 @@ static int dpaa_fq_init(struct dpaa_fq *dpaa_fq, bool td_enable)
		/* Put all the ingress queues in our "ingress CGR". */
		if (priv->use_ingress_cgr &&
		(dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT \|\|
		dpaa_fq->fq_type == FQ_TYPE_RX_ERROR)) {
		dpaa_fq->fq_type == FQ_TYPE_RX_ERROR \|\|
		dpaa_fq->fq_type == FQ_TYPE_RX_PCD)) {
		initfq.we_mask \|= cpu_to_be16(QM_INITFQ_WE_CGID);
		initfq.fqd.fq_ctrl \|= cpu_to_be16(QM_FQCTRL_CGE);
		initfq.fqd.cgid = (u8)priv->ingress_cgr.cgrid;
		@@ -1170,7 +1201,7 @@ static int dpaa_eth_init_tx_port(struct fman_port port, struct dpaa_fq errq,

		static int dpaa_eth_init_rx_port(struct fman_port port, struct dpaa_bp *bps,
		size_t count, struct dpaa_fq *errq,
		struct dpaa_fq *defq,
		struct dpaa_fq defq, struct dpaa_fq pcdq,
		struct dpaa_buffer_layout *buf_layout)
		{
		struct fman_buffer_prefix_content buf_prefix_content;
		@@ -1190,6 +1221,10 @@ static int dpaa_eth_init_rx_port(struct fman_port port, struct dpaa_bp *bps,
		rx_p = &params.specific_params.rx_params;
		rx_p->err_fqid = errq->fqid;
		rx_p->dflt_fqid = defq->fqid;
		if (pcdq) {
		rx_p->pcd_base_fqid = pcdq->fqid;
		rx_p->pcd_fqs_count = DPAA_ETH_PCD_RXQ_NUM;
		}

		count = min(ARRAY_SIZE(rx_p->ext_buf_pools.ext_buf_pool), count);
		rx_p->ext_buf_pools.num_of_pools_used = (u8)count;
		@@ -1234,7 +1269,8 @@ static int dpaa_eth_init_ports(struct mac_device *mac_dev,
		return err;

		err = dpaa_eth_init_rx_port(rxport, bps, count, port_fqs->rx_errq,
		port_fqs->rx_defq, &buf_layout[RX]);
		port_fqs->rx_defq, port_fqs->rx_pcdq,
		&buf_layout[RX]);

		return err;
		}
		@@ -2201,12 +2237,13 @@ static enum qman_cb_dqrr_result rx_default_dqrr(struct qman_portal *portal,
		dma_addr_t addr = qm_fd_addr(fd);
		enum qm_fd_format fd_format;
		struct net_device *net_dev;
		u32 fd_status;
		u32 fd_status, hash_offset;
		struct dpaa_bp *dpaa_bp;
		struct dpaa_priv *priv;
		unsigned int skb_len;
		struct sk_buff *skb;
		int *count_ptr;
		void *vaddr;

		fd_status = be32_to_cpu(fd->status);
		fd_format = qm_fd_get_format(fd);
		@@ -2252,7 +2289,8 @@ static enum qman_cb_dqrr_result rx_default_dqrr(struct qman_portal *portal,
		dma_unmap_single(dpaa_bp->dev, addr, dpaa_bp->size, DMA_FROM_DEVICE);

		/* prefetch the first 64 bytes of the frame or the SGT start */
		prefetch(phys_to_virt(addr) + qm_fd_get_offset(fd));
		vaddr = phys_to_virt(addr);
		prefetch(vaddr + qm_fd_get_offset(fd));

		fd_format = qm_fd_get_format(fd);
		/* The only FD types that we may receive are contig and S/G */
		@@ -2273,6 +2311,18 @@ static enum qman_cb_dqrr_result rx_default_dqrr(struct qman_portal *portal,

		skb->protocol = eth_type_trans(skb, net_dev);

		if (net_dev->features & NETIF_F_RXHASH && priv->keygen_in_use &&
		!fman_port_get_hash_result_offset(priv->mac_dev->port[RX],
		&hash_offset)) {
		enum pkt_hash_types type;

		/* if L4 exists, it was used in the hash generation */
		type = be32_to_cpu(fd->status) & FM_FD_STAT_L4CV ?
		PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3;
		skb_set_hash(skb, be32_to_cpu((u32 )(vaddr + hash_offset)),
		type);
		}

		skb_len = skb->len;

		if (unlikely(netif_receive_skb(skb) == NET_RX_DROP))
		@@ -2511,6 +2561,9 @@ static struct dpaa_bp dpaa_bp_alloc(struct device dev)

		dpaa_bp->bpid = FSL_DPAA_BPID_INV;
		dpaa_bp->percpu_count = devm_alloc_percpu(dev, *dpaa_bp->percpu_count);
		if (!dpaa_bp->percpu_count)
		return ERR_PTR(-ENOMEM);

		dpaa_bp->config_count = FSL_DPAA_ETH_MAX_BUF_COUNT;

		dpaa_bp->seed_cb = dpaa_bp_seed;
		@@ -2738,6 +2791,9 @@ static int dpaa_eth_probe(struct platform_device *pdev)
		if (err)
		goto init_ports_failed;

		/* Rx traffic distribution based on keygen hashing defaults to on */
		priv->keygen_in_use = true;

		priv->percpu_priv = devm_alloc_percpu(dev, *priv->percpu_priv);
		if (!priv->percpu_priv) {
		dev_err(dev, "devm_alloc_percpu() failed\n");

drivers/net/ethernet/freescale/dpaa/dpaa_eth.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -52,6 +52,7 @@
		enum dpaa_fq_type {
		FQ_TYPE_RX_DEFAULT = 1, /* Rx Default FQs */
		FQ_TYPE_RX_ERROR, /* Rx Error FQs */
		FQ_TYPE_RX_PCD, /* Rx Parse Classify Distribute FQs */
		FQ_TYPE_TX, /* "Real" Tx FQs */
		FQ_TYPE_TX_CONFIRM, /* Tx default Conf FQ (actually an Rx FQ) */
		FQ_TYPE_TX_CONF_MQ, /* Tx conf FQs (one for each Tx FQ) */
		@@ -158,6 +159,7 @@ struct dpaa_priv {
		struct list_head dpaa_fq_list;

		u8 num_tc;
		bool keygen_in_use;
		u32 msg_enable; /* net_device message level */

		struct {

drivers/net/ethernet/freescale/dpaa/dpaa_eth_sysfs.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -71,6 +71,9 @@ static ssize_t dpaa_eth_show_fqids(struct device *dev,
		case FQ_TYPE_RX_ERROR:
		str = "Rx error";
		break;
		case FQ_TYPE_RX_PCD:
		str = "Rx PCD";
		break;
		case FQ_TYPE_TX_CONFIRM:
		str = "Tx default confirmation";
		break;

drivers/net/ethernet/freescale/dpaa/dpaa_ethtool.c

+118 −0

Original line number	Diff line number	Diff line
		@@ -399,6 +399,122 @@ static void dpaa_get_strings(struct net_device *net_dev, u32 stringset,
		memcpy(strings, dpaa_stats_global, size);
		}

		static int dpaa_get_hash_opts(struct net_device *dev,
		struct ethtool_rxnfc *cmd)
		{
		struct dpaa_priv *priv = netdev_priv(dev);

		cmd->data = 0;

		switch (cmd->flow_type) {
		case TCP_V4_FLOW:
		case TCP_V6_FLOW:
		case UDP_V4_FLOW:
		case UDP_V6_FLOW:
		if (priv->keygen_in_use)
		cmd->data \|= RXH_L4_B_0_1 \| RXH_L4_B_2_3;
		/* Fall through */
		case IPV4_FLOW:
		case IPV6_FLOW:
		case SCTP_V4_FLOW:
		case SCTP_V6_FLOW:
		case AH_ESP_V4_FLOW:
		case AH_ESP_V6_FLOW:
		case AH_V4_FLOW:
		case AH_V6_FLOW:
		case ESP_V4_FLOW:
		case ESP_V6_FLOW:
		if (priv->keygen_in_use)
		cmd->data \|= RXH_IP_SRC \| RXH_IP_DST;
		break;
		default:
		cmd->data = 0;
		break;
		}

		return 0;
		}

		static int dpaa_get_rxnfc(struct net_device dev, struct ethtool_rxnfc cmd,
		u32 *unused)
		{
		int ret = -EOPNOTSUPP;

		switch (cmd->cmd) {
		case ETHTOOL_GRXFH:
		ret = dpaa_get_hash_opts(dev, cmd);
		break;
		default:
		break;
		}

		return ret;
		}

		static void dpaa_set_hash(struct net_device *net_dev, bool enable)
		{
		struct mac_device *mac_dev;
		struct fman_port *rxport;
		struct dpaa_priv *priv;

		priv = netdev_priv(net_dev);
		mac_dev = priv->mac_dev;
		rxport = mac_dev->port[0];

		fman_port_use_kg_hash(rxport, enable);
		priv->keygen_in_use = enable;
		}

		static int dpaa_set_hash_opts(struct net_device *dev,
		struct ethtool_rxnfc *nfc)
		{
		int ret = -EINVAL;

		/* we support hashing on IPv4/v6 src/dest IP and L4 src/dest port */
		if (nfc->data &
		~(RXH_IP_SRC \| RXH_IP_DST \| RXH_L4_B_0_1 \| RXH_L4_B_2_3))
		return -EINVAL;

		switch (nfc->flow_type) {
		case TCP_V4_FLOW:
		case TCP_V6_FLOW:
		case UDP_V4_FLOW:
		case UDP_V6_FLOW:
		case IPV4_FLOW:
		case IPV6_FLOW:
		case SCTP_V4_FLOW:
		case SCTP_V6_FLOW:
		case AH_ESP_V4_FLOW:
		case AH_ESP_V6_FLOW:
		case AH_V4_FLOW:
		case AH_V6_FLOW:
		case ESP_V4_FLOW:
		case ESP_V6_FLOW:
		dpaa_set_hash(dev, !!nfc->data);
		ret = 0;
		break;
		default:
		break;
		}

		return ret;
		}

		static int dpaa_set_rxnfc(struct net_device dev, struct ethtool_rxnfc cmd)
		{
		int ret = -EOPNOTSUPP;

		switch (cmd->cmd) {
		case ETHTOOL_SRXFH:
		ret = dpaa_set_hash_opts(dev, cmd);
		break;
		default:
		break;
		}

		return ret;
		}

		const struct ethtool_ops dpaa_ethtool_ops = {
		.get_drvinfo = dpaa_get_drvinfo,
		.get_msglevel = dpaa_get_msglevel,
		@@ -412,4 +528,6 @@ const struct ethtool_ops dpaa_ethtool_ops = {
		.get_strings = dpaa_get_strings,
		.get_link_ksettings = dpaa_get_link_ksettings,
		.set_link_ksettings = dpaa_set_link_ksettings,
		.get_rxnfc = dpaa_get_rxnfc,
		.set_rxnfc = dpaa_set_rxnfc,
		};