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Commit 9d43f915 authored by Abhishek Sahu's avatar Abhishek Sahu Committed by Boris Brezillon
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mtd: nand: qcom: enable BAM or ADM mode 



1. DM_EN is only required for EBI2 NAND controller which uses ADM
2. BAM mode will be disabled after power on reset which needs to
   be enabled before starting any BAM transfers.

Reviewed-by: default avatarArchit Taneja <architt@codeaurora.org>
Signed-off-by: default avatarAbhishek Sahu <absahu@codeaurora.org>
Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
parent a86b9c4f

drivers/mtd/nand/qcom_nandc.c

+14 −3
Original line number Original line Diff line number Diff line
@@ -163,6 +163,9 @@ 
#define NAND_DEV_CMD_VLD_VAL		(READ_START_VLD | WRITE_START_VLD | \

#define NAND_DEV_CMD_VLD_VAL		(READ_START_VLD | WRITE_START_VLD | \

					 ERASE_START_VLD | SEQ_READ_START_VLD)

					 ERASE_START_VLD | SEQ_READ_START_VLD)





/* NAND_CTRL bits */

#define	BAM_MODE_EN			BIT(0)



/*

/*

 * the NAND controller performs reads/writes with ECC in 516 byte chunks.

 * the NAND controller performs reads/writes with ECC in 516 byte chunks.

 * the driver calls the chunks 'step' or 'codeword' interchangeably

 * the driver calls the chunks 'step' or 'codeword' interchangeably
@@ -1042,7 +1045,8 @@ static int read_id(struct qcom_nand_host *host, int column) 
	nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);

	nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);

	nandc_set_reg(nandc, NAND_ADDR0, column);

	nandc_set_reg(nandc, NAND_ADDR0, column);

	nandc_set_reg(nandc, NAND_ADDR1, 0);

	nandc_set_reg(nandc, NAND_ADDR1, 0);

	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);

	nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,

		      nandc->props->is_bam ? 0 : DM_EN);

	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);

	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);





	write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);

	write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL);
@@ -2414,12 +2418,19 @@ static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc) 
/* one time setup of a few nand controller registers */

/* one time setup of a few nand controller registers */

static int qcom_nandc_setup(struct qcom_nand_controller *nandc)

static int qcom_nandc_setup(struct qcom_nand_controller *nandc)

{

{

	u32 nand_ctrl;



	/* kill onenand */

	/* kill onenand */

	nandc_write(nandc, SFLASHC_BURST_CFG, 0);

	nandc_write(nandc, SFLASHC_BURST_CFG, 0);

	nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);

	nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);





	/* enable ADM DMA */

	/* enable ADM or BAM DMA */

	if (nandc->props->is_bam) {

		nand_ctrl = nandc_read(nandc, NAND_CTRL);

		nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);

	} else {

		nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);

		nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);

	}





	/* save the original values of these registers */

	/* save the original values of these registers */

	nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);

	nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);