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Commit 9d1677ed authored by Yue Ma's avatar Yue Ma
Browse files

cnss2: Do MHI force wake for shadow register reading 



Unlike shadow register writing, shadow register reading needs MHI in
M0 state. Hence do MHI force wake before reading shadow registers.
Also make sure it is not in atomic context since MHI force wake is
currently not supported it.

Change-Id: I99e9ae1462edc4e805641a5322553b6973074571
Signed-off-by: default avatarYue Ma <yuem@codeaurora.org>
parent 8ee0788f

drivers/net/wireless/cnss2/pci.c

+12 −7
Original line number Diff line number Diff line
@@ -1083,23 +1083,25 @@ int cnss_pci_update_status(struct cnss_pci_data *pci_priv, 
static void cnss_pci_dump_shadow_reg(struct cnss_pci_data *pci_priv)

{

	int i, j = 0, array_size = SHADOW_REG_COUNT + SHADOW_REG_INTER_COUNT;

	gfp_t gfp = GFP_KERNEL;

	u32 reg_offset;



	if (cnss_pci_check_link_status(pci_priv))

	if (in_interrupt() || irqs_disabled())

		return;



	if (in_interrupt() || irqs_disabled())

		gfp = GFP_ATOMIC;

	if (cnss_pci_check_link_status(pci_priv))

		return;



	if (!pci_priv->debug_reg) {

		pci_priv->debug_reg = devm_kzalloc(&pci_priv->pci_dev->dev,

						   sizeof(*pci_priv->debug_reg)

						   * array_size, gfp);

						   * array_size, GFP_KERNEL);

		if (!pci_priv->debug_reg)

			return;

	}



	if (cnss_pci_force_wake_get(pci_priv))

		return;



	cnss_pr_dbg("Start to dump shadow registers\n");



	for (i = 0; i < SHADOW_REG_COUNT; i++, j++) {
@@ -1107,7 +1109,7 @@ static void cnss_pci_dump_shadow_reg(struct cnss_pci_data *pci_priv) 
		pci_priv->debug_reg[j].offset = reg_offset;

		if (cnss_pci_reg_read(pci_priv, reg_offset,

				      &pci_priv->debug_reg[j].val))

			return;

			goto force_wake_put;

	}



	for (i = 0; i < SHADOW_REG_INTER_COUNT; i++, j++) {
@@ -1115,8 +1117,11 @@ static void cnss_pci_dump_shadow_reg(struct cnss_pci_data *pci_priv) 
		pci_priv->debug_reg[j].offset = reg_offset;

		if (cnss_pci_reg_read(pci_priv, reg_offset,

				      &pci_priv->debug_reg[j].val))

			return;

			goto force_wake_put;

	}



force_wake_put:

	cnss_pci_force_wake_put(pci_priv);

}



#ifdef CONFIG_CNSS2_DEBUG