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Commit 9cd39fba authored by Eric Bénard's avatar Eric Bénard Committed by Sascha Hauer
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clock-imx35: fix reboot in internal boot mode 



commit 8d75a262 "ARM: mx35: use generic function for displaying silicon revision"
disabled IIM clock after reading silicon revision which will prevent
reboot in internal boot mode.

Signed-off-by: default avatarEric Bénard <eric@eukrea.com>
Cc: Jason Liu <jason.hui@linaro.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
parent eb444fee

arch/arm/mach-imx/clock-imx35.c

+10 −10
Original line number Original line Diff line number Diff line
@@ -507,7 +507,7 @@ static struct clk_lookup lookups[] = { 




int __init mx35_clocks_init()

int __init mx35_clocks_init()

{

{

	unsigned int cgr2 = 3 << 26, cgr3 = 0;

	unsigned int cgr2 = 3 << 26;





#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)

#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)

	cgr2 |= 3 << 16;

	cgr2 |= 3 << 16;
@@ -521,6 +521,12 @@ int __init mx35_clocks_init() 
	__raw_writel((3 << 18), CCM_BASE + CCM_CGR0);

	__raw_writel((3 << 18), CCM_BASE + CCM_CGR0);

	__raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),

	__raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),

			CCM_BASE + CCM_CGR1);

			CCM_BASE + CCM_CGR1);

	__raw_writel(cgr2, CCM_BASE + CCM_CGR2);

	__raw_writel(0, CCM_BASE + CCM_CGR3);



	clk_enable(&iim_clk);

	imx_print_silicon_rev("i.MX35", mx35_revision());

	clk_disable(&iim_clk);





	/*

	/*

	 * Check if we came up in internal boot mode. If yes, we need some

	 * Check if we came up in internal boot mode. If yes, we need some
@@ -529,16 +535,10 @@ int __init mx35_clocks_init() 
	 */

	 */

	if (!(__raw_readl(CCM_BASE + CCM_RCSR) & (3 << 10))) {

	if (!(__raw_readl(CCM_BASE + CCM_RCSR) & (3 << 10))) {

		/* Additionally turn on UART1, SCC, and IIM clocks */

		/* Additionally turn on UART1, SCC, and IIM clocks */

		cgr2 |= 3 << 16 | 3 << 4;

		cgr3 |= 3 << 2;

	}



	__raw_writel(cgr2, CCM_BASE + CCM_CGR2);

	__raw_writel(cgr3, CCM_BASE + CCM_CGR3);



		clk_enable(&iim_clk);

		clk_enable(&iim_clk);

	imx_print_silicon_rev("i.MX35", mx35_revision());

		clk_enable(&uart1_clk);

	clk_disable(&iim_clk);

		clk_enable(&scc_clk);

	}





#ifdef CONFIG_MXC_USE_EPIT

#ifdef CONFIG_MXC_USE_EPIT

	epit_timer_init(&epit1_clk,

	epit_timer_init(&epit1_clk,