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Commit 9ccd52eb authored by Monk Liu's avatar Monk Liu Committed by Alex Deucher
Browse files

drm/amdgpu:enable mcbp for gfx9(v2) 



set bit 21 of IB.control filed to actually enable
MCBP for SRIOV
v2:
add flag for preemption enable bit for soc15 and use
this flag instead of hardcode.

Signed-off-by: default avatarMonk Liu <Monk.Liu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 806ba2d4

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+3 −0
Original line number Diff line number Diff line
@@ -3073,6 +3073,9 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 


        control |= ib->length_dw | (vm_id << 24);



		if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT))

			control |= INDIRECT_BUFFER_PRE_ENB(1);



        amdgpu_ring_write(ring, header);

	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */

        amdgpu_ring_write(ring,

drivers/gpu/drm/amd/amdgpu/soc15d.h

+1 −0
Original line number Diff line number Diff line
@@ -137,6 +137,7 @@ 
		 * 1 - Stream

		 * 2 - Bypass

		 */

#define     INDIRECT_BUFFER_PRE_ENB(x)		 ((x) << 21)

#define	PACKET3_COPY_DATA				0x40

#define	PACKET3_PFP_SYNC_ME				0x42

#define	PACKET3_COND_WRITE				0x45