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Commit 9cbfc73e authored by Thierry Reding's avatar Thierry Reding
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drm/tegra: hdmi - Disable LVDS mode 



Disable LVDS mode according to register documentation. It seems like
this has no effect on the operation of HDMI, but it's probably a good
idea to do this anyway.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 8c8282c0

drivers/gpu/drm/tegra/hdmi.c

+5 −1
Original line number Diff line number Diff line
@@ -846,9 +846,13 @@ static int tegra_output_hdmi_enable(struct tegra_output *output) 
	tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));

	tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));



	value = 0x1c800;

	value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);

	value &= ~SOR_CSTM_ROTCLK(~0);

	value |= SOR_CSTM_ROTCLK(2);

	value |= SOR_CSTM_PLLDIV;

	value &= ~SOR_CSTM_LVDS_ENABLE;

	value &= ~SOR_CSTM_MODE_MASK;

	value |= SOR_CSTM_MODE_TMDS;

	tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);



	/* start SOR */

drivers/gpu/drm/tegra/hdmi.h

+5 −0
Original line number Diff line number Diff line
@@ -190,6 +190,11 @@ 


#define HDMI_NV_PDISP_SOR_CSTM					0x5a

#define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24)

#define SOR_CSTM_PLLDIV (1 << 21)

#define SOR_CSTM_LVDS_ENABLE (1 << 16)

#define SOR_CSTM_MODE_LVDS (0 << 12)

#define SOR_CSTM_MODE_TMDS (1 << 12)

#define SOR_CSTM_MODE_MASK (3 << 12)



#define HDMI_NV_PDISP_SOR_LVDS					0x5b

#define HDMI_NV_PDISP_SOR_CRCA					0x5c