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Commit 9c6569de authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher
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drm/amd/display: Call validate_fbc should_enable_fbc 



validate_fbc never fails a modeset. It's simply used to decide whether
to use FBC or not. Calling it validate_fbc might be confusing to some so
rename it to should_enable_fbc.

With that let's also remove the DC_STATUS return code and return bool
and make enable_fbc a void function since we never check it's return
value and probably never want to anyways.

Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Reviewed-by: default avatarRoman Li <Roman.Li@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e9be38b4

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+16 −23
Original line number Diff line number Diff line
@@ -1689,60 +1689,54 @@ static void apply_min_clocks( 
/*

 *  Check if FBC can be enabled

 */

static enum dc_status validate_fbc(struct dc *dc,

static bool should_enable_fbc(struct dc *dc,

			      struct dc_state *context)

{

	struct pipe_ctx *pipe_ctx =

			      &context->res_ctx.pipe_ctx[0];

	struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[0];



	ASSERT(dc->fbc_compressor);



	/* FBC memory should be allocated */

	if (!dc->ctx->fbc_gpu_addr)

		return DC_ERROR_UNEXPECTED;

		return false;



	/* Only supports single display */

	if (context->stream_count != 1)

		return DC_ERROR_UNEXPECTED;

		return false;



	/* Only supports eDP */

	if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)

		return DC_ERROR_UNEXPECTED;

		return false;



	/* PSR should not be enabled */

	if (pipe_ctx->stream->sink->link->psr_enabled)

		return DC_ERROR_UNEXPECTED;

		return false;



	/* Nothing to compress */

	if (!pipe_ctx->plane_state)

		return DC_ERROR_UNEXPECTED;

		return false;



	/* Only for non-linear tiling */

	if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)

		return DC_ERROR_UNEXPECTED;

		return false;



	return DC_OK;

	return true;

}



/*

 *  Enable FBC

 */

static enum dc_status enable_fbc(struct dc *dc,

static void enable_fbc(struct dc *dc,

		       struct dc_state *context)

{

	enum dc_status status = validate_fbc(dc, context);



	if (status == DC_OK) {

	if (should_enable_fbc(dc, context)) {

		/* Program GRPH COMPRESSED ADDRESS and PITCH */

		struct compr_addr_and_pitch_params params = {0, 0, 0};

		struct compressor *compr = dc->fbc_compressor;

		struct pipe_ctx *pipe_ctx =

				      &context->res_ctx.pipe_ctx[0];

		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[0];



		params.source_view_width =

				pipe_ctx->stream->timing.h_addressable;

		params.source_view_height =

				pipe_ctx->stream->timing.v_addressable;

		params.source_view_width = pipe_ctx->stream->timing.h_addressable;

		params.source_view_height = pipe_ctx->stream->timing.v_addressable;



		compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
@@ -1751,7 +1745,6 @@ static enum dc_status enable_fbc(struct dc *dc, 


		compr->funcs->enable_fbc(compr, &params);

	}

	return status;

}

#endif