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Commit 9b7ff0c6 authored by Nicholas Piggin's avatar Nicholas Piggin Committed by Michael Ellerman
Browse files

powerpc/64s: Add SCV FSCR bit for ISA v3.0 



Add the bit definition and use it in facility_unavailable_exception() so we can
intelligently report the cause if we take a fault for SCV. This doesn't actually
enable SCV.

Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
[mpe: Drop whitespace changes to the existing entries, flush out change log]
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 794464f4

arch/powerpc/include/asm/reg.h

+2 −0
Original line number Diff line number Diff line
@@ -310,6 +310,7 @@ 
#define SPRN_PMCR	0x374	/* Power Management Control Register */



/* HFSCR and FSCR bit numbers are the same */

#define FSCR_SCV_LG	12	/* Enable System Call Vectored */

#define FSCR_MSGP_LG	10	/* Enable MSGP */

#define FSCR_TAR_LG	8	/* Enable Target Address Register */

#define FSCR_EBB_LG	7	/* Enable Event Based Branching */
@@ -320,6 +321,7 @@ 
#define FSCR_VECVSX_LG	1	/* Enable VMX/VSX  */

#define FSCR_FP_LG	0	/* Enable Floating Point */

#define SPRN_FSCR	0x099	/* Facility Status & Control Register */

#define   FSCR_SCV	__MASK(FSCR_SCV_LG)

#define   FSCR_TAR	__MASK(FSCR_TAR_LG)

#define   FSCR_EBB	__MASK(FSCR_EBB_LG)

#define   FSCR_DSCR	__MASK(FSCR_DSCR_LG)

arch/powerpc/kernel/traps.c

+1 −0
Original line number Diff line number Diff line
@@ -1441,6 +1441,7 @@ void facility_unavailable_exception(struct pt_regs *regs) 
		[FSCR_EBB_LG] = "EBB",

		[FSCR_TAR_LG] = "TAR",

		[FSCR_MSGP_LG] = "MSGP",

		[FSCR_SCV_LG] = "SCV",

	};

	char *facility = "unknown";

	u64 value;