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Commit 9b471446 authored by Jesse Brandeburg's avatar Jesse Brandeburg Committed by David S. Miller
Browse files

ixgbe: use EIAM to automask MSI-X 



when disabling interrupts, driver was writing with IO, this is no
necessary because on ixgbe parts the hardware can "oneshot"
disable and clear the interrupt.  So on 82598/82599 use of EIAM
should avoid one posted write per interrupt when in MSI-X mode.
This should improve performance and seems to in my limited
testing, reduce CPU utilization VERY slightly.

Signed-off-by: default avatarJesse Brandeburg <jesse.brandeburg@intel.com>
Acked-by: default avatarPeter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 7ca3bc58

drivers/net/ixgbe/ixgbe_main.c

+19 −6
Original line number Diff line number Diff line
@@ -1329,8 +1329,7 @@ static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) 
		                      r_idx + 1);

	}



	/* disable interrupts on this vector only */

	ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));

	/* EIAM disabled interrupts (on this vector) for us */

	napi_schedule(&q_vector->napi);



	return IRQ_HANDLED;
@@ -1362,7 +1361,7 @@ static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) 
		return IRQ_HANDLED;



	/* disable interrupts on this vector only */

	ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));

	/* EIAM disabled interrupts (on this vector) for us */

	napi_schedule(&q_vector->napi);



	return IRQ_HANDLED;
@@ -1397,8 +1396,7 @@ static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) 
		                      r_idx + 1);

	}



	/* disable interrupts on this vector only */

	ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));

	/* EIAM disabled interrupts (on this vector) for us */

	napi_schedule(&q_vector->napi);



	return IRQ_HANDLED;
@@ -2716,7 +2714,22 @@ static int ixgbe_up_complete(struct ixgbe_adapter *adapter) 
		IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);

	}



	if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {

	if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {

		/*

		 * use EIAM to auto-mask when MSI-X interrupt is asserted

		 * this saves a register write for every interrupt

		 */

		switch (hw->mac.type) {

		case ixgbe_mac_82598EB:

			IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);

			break;

		default:

		case ixgbe_mac_82599EB:

			IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);

			IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);

			break;

		}

	} else {

		/* legacy interrupts, use EIAM to auto-mask when reading EICR,

		 * specifically only auto mask tx and rx interrupts */

		IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);