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Commit 9b3b80b7 authored by Vipin Deep Kaur's avatar Vipin Deep Kaur
Browse files

ARM: dts: msm: Add QUPV3 SE DT nodes for HSUART on kona 



Add initial device tree nodes for QUPV3 HSUART instances.

Change-Id: I7e42c13b91cd5ce42bcde42de3b158d482b60e2d
Signed-off-by: default avatarVipin Deep Kaur <vkaur@codeaurora.org>
Signed-off-by: default avatarMukesh Kumar Savaliya <msavaliy@codeaurora.org>
parent 3b3e314b

arch/arm64/boot/dts/qcom/kona-qupv3.dtsi

+73 −1
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
 */



#include <dt-bindings/msm/msm-bus-ids.h>

#include <dt-bindings/interrupt-controller/irq.h>



&soc {

	/* QUPv3_0  wrapper  instance : North QUP*/
@@ -35,9 +36,34 @@ 
		pinctrl-1 = <&qupv3_se2_2uart_sleep>;

		interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;

		qcom,wrapper-core = <&qupv3_0>;

		qcom,change-sampling-rate;

		status = "disabled";

	};



	/*

	 * HS UART instances. HS UART usecases can be supported on these

	 * instances only.

	 */

	qupv3_se6_4uart: qcom,qup_uart@998000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0x998000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,

							<&qupv3_se6_tx>;

		pinctrl-1 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,

							<&qupv3_se6_tx>;

		interrupts-extended = <&pdc 607 IRQ_TYPE_LEVEL_HIGH>,

					<&tlmm 19 0>;

		status = "disabled";

		qcom,wakeup-byte = <0xFD>;

		qcom,wrapper-core = <&qupv3_0>;

	};



		/* I2C */

	qupv3_se0_i2c: i2c@980000 {

		compatible = "qcom,i2c-geni";
@@ -243,6 +269,7 @@ 
		pinctrl-1 = <&qupv3_se12_2uart_sleep>;

		interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;

		qcom,wrapper-core = <&qupv3_1>;

		qcom,change-sampling-rate;

		status = "disabled";

	};
@@ -382,6 +409,50 @@ 
		};

	};



	/*

	 * HS UART : Modem/Audio backup

	 */

	qupv3_se17_4uart: qcom,qup_uart@88c000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0x88c000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>,

				<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,

				<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,

							<&qupv3_se17_tx>;

		pinctrl-1 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,

							<&qupv3_se17_tx>;

		interrupts-extended = <&pdc 585 IRQ_TYPE_LEVEL_HIGH>,

					<&tlmm 55 0>;

		status = "disabled";

		qcom,wakeup-byte = <0xFD>;

		qcom,wrapper-core = <&qupv3_2>;

	};



	/*

	 * HS UART : 2-wire Modem

	 */

	qupv3_se18_2uart: qcom,qup_uart@890000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0x890000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>,

				<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,

				<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se18_rx>, <&qupv3_se18_tx>;

		pinctrl-1 = <&qupv3_se18_rx>, <&qupv3_se18_tx>;

		interrupts-extended = <&pdc 586 IRQ_TYPE_LEVEL_HIGH>,

						<&tlmm 59 0>;

		status = "disabled";

		qcom,wakeup-byte = <0xFD>;

		qcom,wrapper-core = <&qupv3_2>;

	};



	/* I2C */

	qupv3_se14_i2c: i2c@880000 {

		compatible = "qcom,i2c-geni";
@@ -502,4 +573,5 @@ 
		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};



};